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PDF UPA1724 Data sheet ( Hoja de datos )
| Número de pieza | UPA1724 | |
| Descripción | SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1724
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
5 DESCRIPTION
The µPA1724 is N-Channel MOS Field Effect
Transistor designed for power management
applications of notebook computers and so on.
FEATURES
• 2.5-V gate drive and low on-resistance
RDS(on)1 = 11.0 mΩ MAX. (VGS = 4.5 V, ID = 5.0 A)
5 RDS(on)2 = 12.0 mΩ MAX. (VGS = 4.0 V, ID = 5.0 A)
RDS(on)3 = 15.0 mΩ MAX. (VGS = 2.5 V, ID = 5.0 A)
• Low Ciss: Ciss = 1850 pF TYP.
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
µPA1724G
Power SOP8
PACKAGE DRAWING (Unit : mm)
85
1,2,3 ; Source
4 ; Gate
5,6,7,8 ; Drain
14
5.37 MAX.
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS 20 V
Gate to Source Voltage (VDS = 0 V)
VGSS ±12 V
Drain Current (DC)
ID(DC)
±10
A
Drain Current (pulse) Note1
ID(pulse)
±40
A
Total Power Dissipation (TA = 25°C) Note2
PT
2.0 W
Channel Temperature
Tch 150 °C
Storage Temperature
Tstg –55 to +150 °C
EQUIVALENT CIRCUIT
Drain
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G14048EJ1V0DS00 (1st edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999, 2000
1 page  
µ PA1724
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
Mounted on ceramic
2.4
substrate of
1200 mm 2×2.2 mm
2.0
1.6
1.2
0.8
0.4
0
0 20 40 60 80 100 120 140 160
TA - Ambient Temperature - ˚C
100
10
1
FORWARD BIAS SAFE OPERATING AREA
ID(pulse) = 40 A
RDS(oVn)GLSim=i4te.5d V)
(@
ID(DC) = 10 A
PW
1 ms = 100 µs
10 ms
Power
100 ms
Dissipation Limited
TA = 25 ˚C
0.1 Single Pulse
0.1 1
10 100
VDS - Drain to Source Voltage - V
Remark
Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
1 000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100 Rth(ch-A) = 62.5˚C/W
10
1
0.1
0.01
0.001
10 µ
100µ
1m
10 m 100 m
Mounted on ceramic
substrate of 1200 mm2× 2.2 mm
Single Pulse
1 10 100 1 000
PW - Pulse Width - s
Data Sheet G14048EJ1V0DS00
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPA1724.PDF ] | |
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