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PDF PCD5096H Data sheet ( Hoja de datos )

Número de pieza PCD5096H
Descripción Universal codec
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
PCD5096
Universal codec
Preliminary specification
File under Integrated Circuits, IC17
1997 Jan 22

1 page




PCD5096H pdf
Philips Semiconductors
Universal codec
Preliminary specification
PCD5096
6 PINNING INFORMATION
6.1 Pin description
Table 1 QFP44 package
SYMBOL
IO0
IO1
CLK
VDD_PLL
VSS_PLL
VSS_1
VDD_1
SCL
SDA
A0
A1
LIFM_DA1
LIFP_DA1
VDDA_1
LIFM_AD1
LIFP_AD1
VSSA_1
MICM1
MICP1
VREF1
VBGP
VREF2
VMIC_HS
MICP_HS
MICM_HS
VMIC_HF
MICP_HF
MICM_HF
VSSA_2
LIFP_AD2
LIFM_AD2
VDDA_2
EARP_HS
EARM_HS
EARP_HF
EARM_HF
TEST
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I/O(1)
I/O
I/O
I
P
P
P
P
I
I/O
I
I
O
O
P
I
I
P
I
I
O
O
O
O
I
I
O
I
I
P
I
I
P
O
O
O
O
I
DESCRIPTION
programmable I/O pin 0 (Schmitt trigger input, pull-up output)
programmable I/O pin 1 (Schmitt trigger input, pull-up output)
clock input
3 V analog supply for PLL
analog ground supply for PLL
peripheral ground supply
3 to 5 V peripheral supply
I2C-bus clock signal input (Schmitt trigger)
I2C-bus data signal
I2C-bus subaddress
I2C-bus subaddress
negative analog output from Codec 1 to line interface
positive analog output from Codec 1 to line interface
3 V analog supply for Codec 1
negative analog input to Codec 1 from line interface
positive analog input to Codec 1 from line interface
analog ground supply for Codec 1
negative analog input to Codec 1 from microphone
positive analog input to Codec 1 from microphone
Codec 1 analog reference voltage
bandgap analog output voltage
Codec 2 analog reference voltage
positive analog supply voltage from Codec 2 for handset microphone
positive analog input to Codec 2 from handset microphone
negative analog input to Codec 2 from handset microphone
positive analog supply voltage from Codec 2 for hands-free microphone
positive analog input to Codec 2 from hands-free microphone
negative analog input to Codec 2 from hands-free microphone
analog ground supply for Codec 2
positive analog input to Codec 2 from line interface
negative analog input to Codec 2 from line interface
3 V analog supply for Codec 2
positive analog output from Codec 2 to handset earpiece
negative analog output from Codec 2 to handset earpiece
positive output to hands-free earpiece
negative output to hands-free earpiece
test input; pull-down
1997 Jan 22
5

5 Page





PCD5096H arduino
Philips Semiconductors
Universal codec
Preliminary specification
PCD5096
After reset, all the flip-flops are in a defined state, and the
IOM, DSP and codecs are in inactive mode. In typical
applications the universal codec is used with the
PCD5093, which provides a clock (GP_CLK7) and a reset
signal to the universal codec. The reset signal must be
generated by a microcontroller port bit. The RESET_OUT
pin of the PCD5093 cannot be used for this purpose,
because GP_CLK7 is stopped while RESET_OUT is LOW
after a Power-on-reset.
8 MEMORY AND CONTROL REGISTERS
8.1 DSP memories
The DSP in the PCD5096 has access to a 4k × 24-bit DSP
program ROM, a 512 × 16-bit XRAM and a 512 × 16-bit
YRAM.
8.2 Data memory and control register map
The PCD5096 contains a 128 word (128 × 16-bit) System
Data RAM (SDR) and a group of 7 control registers
mapped onto the upper addresses of the SDR.
The registers and the SDR are byte and word accessible
externally, via the I2C-bus interface and internally via the
internal system bus.
The memory map is shown in Fig.6. The lower 32 words
contain the DSP parameter table. The next 32 words are
reserved for the IOM control table, which is used to control
the activity on the IOM-2 interface (maximum 32 slots per
8 kHz speech frame). The rest of the SDR addressable
space (40H to 77H) is free RAM and can be used to store
up to 14 IOM data buffer pairs. In cases where not all
14 IOM buffer pairs are needed this memory space can be
used for other applications via the I2C-bus. The same
holds for the unused part of the IOM control table.
The upper addresses of the SDR (78H to 7EH) are
mapped onto 7 control registers (CR0 to CR6) that control
the entire chip (DSP mode, data rate on the IOM-2
interface, control of the two codecs).
Note that the uppermost address of the SDR (7FH) is not
mapped to any hardware register and is addressable as a
normal RAM word.
The contents of the IOM control table and the IOM data
buffers are described in Chapter 9. For further details
about the DSP parameter table, see the “PCD5096 DSP
user manual”.
handbook, full pagewidth
1997 Jan 22
7FH free RAM
7EH
control registers
78H (7 words)
77H
SDR
hardware registers
IOM data buffers
and
free RAM
(14 x 4 words)
40H
3FH
IOM control table
(32 words)
20H
1FH
DSP parameter table
(32 words)
00H
MBH865
SDR
Fig.6 PCD5096 Memory map.
11

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