PDF UMA1016AT Data sheet ( Hoja de datos )

Número de pieza	UMA1016AT
Descripción	Frequency synthesizer for radio communication equipment
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET UMA1016xT Frequency synthesizer for radio communication equipment Product speciﬁcation Supersedes data of June 1992 File under Integrated Circuits, IC03 1995 Jul 12 1 page Philips Semiconductors Frequency synthesizer for radio communication equipment Product speciﬁcation UMA1016xT Oscillator External capacitive feedback is applied to the common collector Colpitts oscillator which has high voltage supply rejection and negligible temperature drift. It is designed to function as an input buffer without the need for external components when a TCXO or other clock is used. A separate output buffer, which remains active during power-down (HPDN taken LOW), provides a TTL compatible signal to drive external logic circuits (REFCK). Reference divider The reference divider has a fixed divider ratio set by metal masking between 2 and 31. For example, a 4 MHz crystal connected to the oscillator and a ÷16 ratio allows a channel spacing of 250 kHz. Other frequencies and ratios are possible. Phase comparator The phase comparator combines a phase and frequency detector and charge pump (see Fig.3). The charge pump current is internally fixed and determined for fast switching. It is compensated against power supply and temperature variation. The detector is assembled from dual D-type flip-flops which, together with feedback, remove the ‘dead’ zone. Upon the detection of a phase error, either UP or DO go HIGH. This gates the appropriate current generator to source or sink 1.75 mA at the output pin. When no phase error is detected, CP becomes 3-state. The tuning voltage of the VCO is established from the sum of the current pulses into the loop filter. A simple passive loop filter may be used to offer high performance without requiring an operational-amp. The phase comparator function is summarized in Table 2. Main control interface The programming control interface permits access to two internal latches, denoted Tx and Rx. The serial input bits on DATA, entered MSB first, are converted to a parallel word and stored in the appropriate latch under the control of the last entered register bit (PB0). When this is set HIGH, data serially fed to the register is loaded into the transmit (Tx) latch; when PB0 is LOW, the data is transferred to the receive latch (Rx). The data sent to the synthesizer is loaded in bursts framed by the signal EN. Programming clock edges, together with their appropriate data bits, are ignored until EN becomes active (LOW). The internal latches are updated with the latest programming data when EN returns inactive (HIGH). Only the last 15 bits serially clocked into the device are retained within the programming register. One extra shift register bit (PB7) can be internally added via metal masking to allow direct software compatibility with a 7-bit swallow counter and a 64/65 dual-modulus prescaler. No check is made on the number of clock pulses received during the time that programming is enabled. EN going HIGH while CLOCK is still LOW generates an active clock edge causing a shift of the data bits. Data programmed into the register is lost during power-down (HPDN taken LOW). The maximum serial bus clock speed is specified as 5 MHz. Minimum speed is limited by the clock edge rise and fall times to ensure that no data transparency condition can exist. Independent of any serial programming activity, the RF divider chain uses the data previously stored within the selected latch to determine the synthesized channel frequency. The Tx/Rx signal controls which latch is read to preload the counter bits at each division cycle. When new data is updated into the device, it is used during the cycle following latch selection by the Tx/Rx control line. If the Tx/Rx line is tied LOW, only data loaded into the Rx latch is used. In this event the serial data stream clocked into the synthesizer must terminate with an ‘0’. The logic diagram for the first bits of the programming interface is shown in Fig.3. The other bits are processed in a similar manner by a further 9 stages of the shift register-latches-multiplexer. The signals supplied to the circuit are described by the timing diagram. The table of values has been specified for maximum bus speed. Under slow clocking conditions, rise and fall times must not be excessively slow. 1995 Jul 12 5 5 Page Philips Semiconductors Frequency synthesizer for radio communication equipment Product speciﬁcation UMA1016xT SYMBOL PARAMETER CONDITIONS Interface logic input signal levels (HPDN, EN, DATA, CK, Tx/Rx) VIH VIL(PD) VIL Ibias HIGH level input voltage LOW level input voltage LOW level input voltage input bias current all inputs HPDN except HPDN logic 1 logic 0 Ci input capacitance indicative; not tested Oscillator buffered logic output signal (REFCK) Voh Vol Io(sink) tr tf HIGH level driven output voltage LOW level driven output voltage output sink current reference clock output rise time reference clock output fall time VDD = 5 V VCL = 0.5 V CI = 25 pF CL = 25 pF MIN. TYP. MAX. UNIT 3− −0.3 − −0.3 − −− −5 − −3 VDD + 0.3 V 0.6 V 1V 5 µA − µA − pF 3.5 4.0 0− −0.4 − − 50 − 50 VDD − 0.5 V 0.4 V − mA − ns − ns 1995 Jul 12 11 11 Page

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