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PDF UMA1002 Data sheet ( Hoja de datos )
| Número de pieza | UMA1002 | |
| Descripción | Data processor for cellular radio DPROC2 | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
UMA1002
Data processor for cellular radio
(DPROC2)
Product specification
Supersedes data of 1996 Sep 13
File under Integrated Circuits, IC17
1997 Jan 28
1 page  
Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
SYMBOL
PIN
SO28 LQFP32
DESCRIPTION
TXCTRL
INVTX
TSCAN
A0
SDA
SCL
n.c.
RXCLK
VDDD
VDDA
MVO
JTACS
CLKSEL
20 19 Transmitter control open-drain output used to disable the transmitter during an
RECC access failure. Output level LOW means RF disabled.
21 21 This input inverts the sense of transmitted data stream, which allows RF
modulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the modulated data stream depends on
the transmitter local oscillator. Input LOW means data inverted.
22 22 Test switch input, only enabled if TST = logic 1, but should have a defined state.
23 23 Input to select the least significant bit of the I2C-bus address.
24 24 Serial data input/output (I2C-bus).
25 25 Serial clock input (I2C-bus).
26 18 Not connected.
27 26 Received data clock input from the system controller.
28 27 Digital supply voltage (+3 V).
− 28 Analog supply voltage (+3 V).
− 3 Majority voting output indicating that on FOCC the first 3 received words do not
differ from each other and thus the majority decision over 5 words can already be
carried out. Because of the required speed, indication is at this pin (and not via the
I2C-bus) which can be monitored by the system controller. Output LOW means the
receiver can be switched off.
− 6 Digital input signal for JTACS, input HIGH means that data is routed from TXLINE
directly without processing to gated D/A converter (if enabled by STEN bit).
− 20 Input switch for internal divide-by-8 or divide-by-1 divider between CLKIN and
CLKOUT (internal pull-down → divide-by-1 is default if not bonded out in SO28
package).
Note
1. Must not be connected in existing applications.
1997 Jan 28
5
5 Page 
Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
Table 4 Description of I2C-bus register map
REGISTER
BITS
LOGIC LEVEL
DESCRIPTION
Control Register 1
BUFEN
SERV
STS(1)
TXRST
0
1
0
1
0
1
1
ABREN
FVC(2)
STEN
SATEN
1
0
0
1
0
1
0
1
1.2 MHz signal not available at pin CLKOUT
1.2 MHz signal is available at pin CLKOUT
serving system data stream B selected
serving system data stream A selected
TACS selected
AMPS selected
terminates a message being transmitted on the reverse channel; monostable
signal causing a reset of the message transmission circuitry and resets the
I2C-bus bits TXABRT, TXIP and clears the transmit buffer
DPROC2 has permission to abort data transmission and disable RF on the RECC
following the detection of a channel access attempt collision
no permission for above operations
control channel format selected
voice channel format selected
disables output of signalling tone to pin DATA
enables output of signalling tone to pin DATA if FVC = logic 1
disables output of SAT transponded signal to pin DATA
enables output of SAT transponded signal to pin DATA if FVC = logic 1
Control Register 2
MAJ
0
1
MR0, MR1
see Table 5
DBCH
DCFM
ENSM
ESCC0,
ESCC1
see Table 8
see Table 8
0
1
see Table 6
Status Register
WSYNC
0
1
majority voting procedure on FOCC using all 5 frame words, MVO output is always
HIGH
majority voting procedure on FOCC using the first 3 frame words, if they are all
identical the MVO pin goes LOW (see Fig.6)
determines set-up time of MVO signal with respect to beginning of the next dotting
(see Fig.6)
BCH error filter
control filler message filter
enable SAT monitoring; ESCC bits are not used
enable SAT monitoring; ESCC bits are used for following function
expected SAT colour code bits; the incoming SAT is compared to these bits, the
result (expected or not expected SAT frequency) is given out by the BUSY/VSAT
pin (when FVC = logic 1), which prevents periodical reading from the I2C-bus
status register
DPROC2 has not acquired frame synchronization in accordance with FOCC
format
DPROC2 has acquired frame synchronization in accordance with FOCC format
1997 Jan 28
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet UMA1002.PDF ] | |
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