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PDF PCD5042 Data sheet ( Hoja de datos )

Número de pieza PCD5042
Descripción DECT burst mode controller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCD5042 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
PCD5042
DECT burst mode controller
Objective specification
File under Integrated Circuits, IC17
1996 Oct 31

1 page




PCD5042 pdf
Philips Semiconductors
DECT burst mode controller
Objective specification
PCD5042
SYMBOL
INT
CLK100
VSS3
DO
FS3
FS1
FS4
FS2
DI
DCK
CLK3
ANT_SW
T_ENABLE
T_POWER_RMP
RMT_STAT
SYNTH_LOCK
VSS4
REF_CLK
VDD2
S_ENABLE
S_CLK
S_DATA
S_POWER_DWN
VCO_BND_SW
1200 HZ
T_DATA
SET_OFF_IN
TEST1
RSSI_AN
TEST2
TEST3
R_DATA
PIN
TYPE(2)
QFP64 LQFP80(1)
DESCRIPTION
24 27 O interrupt (active LOW)
25 29 O 100 Hz frame timer
26 31 P negative supply 3
27 32 O 3-state data output on the speech interface
33 I/O 8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
28 34 I/O 8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
35 I/O 8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
29 36 O 8 kHz framing signal to ADPCM CODEC 2 in the base station
mode
30 37 I data input on the speech interface
31 38 O simple base + handset; 1152 kHz data clock (output),
otherwise 2048 kHz data clock (input) signal
32 39 O 3.456 MHz clock (nominal value, used to adjust system
timing)
33 40 O selects one of two antennas
34 41 O Transmitter Enable (active LOW)
35 43 O Transmitter Power Ramp control
36 44 I serial 8-bit data can be read in for each slot; REMote radio
37 45 I lock indication from synthesizer
38 46 P negative supply 4
39 47 O reference frequency for the synthesizer, i.e. the crystal
oscillator clock fCLK
40 48 P positive supply 2
41 49 O synthesizer enable
42 51 O clock signal, to be used with S_DATA
43 52 O serial data to the synthesizer
44 53 O synthesizer power-down control
45 54 O VCO bandswitch control signal
46 55 O control signal for dual synthesizer schemes
47 56 O serial output data to transmitter
48 57 I switches off the crystal oscillator, and prevents all RF signals
from becoming active
49 58 I selects various test modes.; normal operation set to 0
50 60 I analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
51 I selects various test modes; normal operation set to 0
52 61 I selects various test modes; normal operation set to 0
53 63 I receive data
1996 Oct 31
5

5 Page





PCD5042 arduino
Philips Semiconductors
DECT burst mode controller
Objective specification
PCD5042
data, these disturbances are not audible (or are less
audible) to the user. The PCD5042 performs two types of
muting:
Fast muting
Slow muting.
Fast muting, which is performed by the PCD5042
automatically, is nothing more than a repetition of the
previously received frame (80 speech samples) to the
ADPCM CODEC. It is issued if no Sync word was
detected. Slow muting is issued by the microcontroller,
after having detected a degradation of quality. A slow mute
is implemented as a continuous ‘0000’ nibble transmission
to the ADPCM CODEC, until slow mute is released.
6.4.4 LOCAL CALL
A local call option is implemented, in order to loopback
data from one CODEC to another CODEC, and vice versa,
see Fig.5.
handbook, halfpage
01
01
DO
speech buffer
pair
01
01
DI
speech slots
MBH710
Fig.5 Local call switching on speech interface.
6.5 RF interface
Most of the functions performed by the RF interface are
under control of the PCC. Specifically, the processing of
non-speech data and the programming of functions and
registers is done via the PCC.
6.5.1 SERIAL RECEIVER
The serial receiver processes the data, which comes from
the RF section, and which is already filtered by the
synchronization part. The data is latched, using the
recovered data clock.
The serial receiver will collect the complete A-field and
B-field and store it in the common data memory. Before the
A-field is received, the A-field start address is programmed
by the PCC. Upon reception of A-field nibbles, the address
is updated by the serial receiver. Meanwhile, the PCC will
program the B-field start address.
In Fig.6 the data flow in the serial receiver is shown. Note
that almost no decoding of messages is required. Only the
header of the A-field needs to be decoded to check if a
ciphered message is being received or transmitted, which
requires the ciphering to be switched on in the A-field also.
6.5.2 SERIAL TRANSMITTER
The serial transmitter performs the reverse of the receiver
functions. Several blocks used in the receiver are also
used in the transmitter. Amongst these are the
CRC-generators, the scrambler, and the address
registers. Figure 7 shows the serial transmitter structure.
By transmitting the X-CRC twice, the Z-field is transmitted.
The handling of the address registers is the same for the
transmitter. Transmission of the synchronization sequence
(S-field) is done using the same method as the A-field and
B-field. The S-field is stored in the common data memory
and will be fetched by the transmitter, just before
transmission.
Two additional functions are not shown in Fig.7:
In the handset the data in the serial transmitter may be
advanced by a programmable number of bit periods.
This is done to compensate for the delay in the RF
section
The transmitted data can be inverted (using a switch in
the PCD5042 mode register), in order to connect the
PCD5042 to VCOs requiring negative modulation.
1996 Oct 31
11

11 Page







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