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PDF PCD5002H Data sheet ( Hoja de datos )

Número de pieza PCD5002H
Descripción Advanced POCSAG and APOC-1 Paging Decoder
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
PCD5002
Advanced POCSAG and APOC-1
Paging Decoder
Product specification
Supersedes data of 1997 Mar 04
File under Integrated Circuits, IC17
1997 Jun 24

1 page




PCD5002H pdf
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
7 PINNING
SYMBOL PIN
DESCRIPTION
ATL 1 alert LOW level output
ALC 2 alert control input
(normally LOW by internal pull-down)
DON
3 direct ON/OFF input
(normally LOW by internal pull-down)
REF
4 real time clock frequency reference
output
INT 5 interrupt output
n.c. 6 not connected
RST
7 reset input
(normally LOW by internal pull-down)
VPR
SDA
SCL
8 external positive voltage reference
input
9 I2C-bus serial data input/output
10 I2C-bus serial clock input
VDD
VSS
VPO
CCP
11 main positive supply voltage
12 main negative supply voltage
13 voltage converter positive output
14 voltage converter shunt capacitor
(positive side)
CCN
15 voltage converter shunt capacitor
(negative side)
TS1 16 test input 1
(normally LOW by internal pull-down)
XTAL2 17 decoder crystal oscillator output
XTAL1 18 decoder crystal oscillator input
n.c. 19 not connected
TS2 20 test input 2
(normally LOW by internal pull-down)
BAT 21 battery sense input
n.c. 22 not connected
RDI 23 received data input
(POCSAG or APOC-1)
RXE
24 receiver circuit enable output
ROE
25 receiver oscillator enable output
ZSD
26 synthesizer serial data output
ZSC
27 synthesizer serial clock output
ZLE 28 synthesizer latch enable output
VSS 29 main negative supply voltage
VIB 30 vibrator motor drive output
LED 31 LED drive output
ATH 32 alert HIGH level output
1997 Jun 24
5
ATL 1
ALC 2
DON 3
REF 4
INT 5
n.c. 6
RST 7
VPR 8
PCD5002H
24 RXE
23 RDI
22 n.c.
21 BAT
20 TS2
19 n.c.
18 XTAL1
17 XTAL2
MGD080
Fig.2 Pin configuration for SOT358-1 (LQFP32).

5 Page





PCD5002H arduino
Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
handbook, full pagewidth
OFF to ON status
preamble
switch on
sync word
no preamble
or sync word
(3 batches)
carrier detect
preamble
sync word
TX off
time out
preamble receive 1 preamble
no preamble (1 batch)
long fade recovery
sync word
preamble
batch zero detect
batch zero ID
sync word
no sync word
batch zero identify
no batch zero ID
batch
zero ID
cycle receive
sync
no sync
word
word
preamble
short fade recovery
no sync word
or preamble
sync word
transmitter off
no preamble
TX off time out
(1 batch)
preamble
sync word
preamble receive 2
MGD269
Fig.5 APOC-1 synchronization algorithm.
8.14 APOC-1 synchronization strategy
The synchronization strategy in APOC-1 is an extended
version of the ACCESS® scheme and is illustrated in Fig.5.
The PCD5002 counts the number of batches in a
transmission, starting from the first batch received after
preamble. Counter overflow occurs due to the size of a
cycle, as determined by SPF programming.
Initially, after switching to the ON status, the decoder will
be in the switch-on mode. Here the receiver will be
enabled for up to 3 batches, testing for preamble and sync
word. Detection of preamble causes the device to switch
to the ‘preamble receive’ mode, while any enabled sync
word enters the ‘batch zero detect’ mode. Failure to detect
either will cause the device to switch to the ‘carrier detect’
mode.
In the preamble receive 1 mode the PCD5002 searches
for a sync word, the receiver remaining enabled while
preamble is detected. As soon as an enabled sync word is
found the ‘batch zero identify’ mode is started.
If preamble is not found within one batch duration then the
‘long fade recovery’ mode is entered.
When in batch zero detect mode the PCD5002 switches
on every batch to maintain synchronization and check for
the batch zero identifier. Detection of the batch zero
identifier activates the ‘cycle receive’ mode. When
synchronization is lost the ‘long fade recovery’ mode is
entered. ‘preamble receive’ mode is entered when
preamble is detected.
In the batch zero identify mode the first codeword
immediately after the sync word of the first batch is
compared with the programmed batch zero identifier.
Failure to detect the batch zero identifier will cause the
device to enter the ‘short fade recovery’ mode.
When this comparison is successful the function bits
determine whether any broadcast message will follow.
Any function bit combination other than ‘1,1’ will cause the
PCD5002 to accept message codewords until terminated
by a valid address codeword.
1997 Jun 24
11

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