PDF PCD3360P Data sheet ( Hoja de datos )

Número de pieza	PCD3360P
Descripción	Programmable multi-tone telephone ringer
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET PCD3360 Programmable multi-tone telephone ringer Product speciﬁcation Supersedes data of August 1985 File under Integrated Circuits, IC03 1997 Jan 15 1 page Philips Semiconductors Programmable multi-tone telephone ringer Product speciﬁcation PCD3360 7 FUNCTIONAL DESCRIPTION (see Fig.1) 7.1 Supply pins (VDD and VSS) If the supply current (VDD) drops below the standby voltage (Vstb), the oscillator and most other functions are switched off and the supply current is reduced to the standby current (Istb). The automatic swell register retains its information until VDD drops further to a value VAS at which reset occurs. 7.2 Oscillator (OSC) The 64 kHz oscillator is operated via an external resistor and capacitor connected to pin OSC (see Fig.8). The oscillator signal is divided by two to provide the 32 kHz internal system clock. 7.3 Selection pin input circuit (see Fig.3) Pins FDE, RR1, RR2, DM, IS1, IS2, TS1, TS2, FL and FH are pulled down internally by a pull-down current IIH when they are connected to VDD and by a pull-down resistance RIL when they are connected to VSS. Thus when the pins are open-circuit they are defined LOW. Therefore only a single-contact switch is required to connect the pins to VDD; yet the supply current is only marginally increased as IIH is very small. selection pins FDE RR1 RR2 DM IS1 IS2 TS1 TS2 FL FH IIH (1) VSS PCD3360 MGD709 7.4 Frequency discriminator circuit (FDE and FDI) The frequency discriminator circuit prevents the ringer being activated unintentionally by dial pulses, speech or other invalid signals. The circuit is enabled or disabled by input FDE. When FDE is LOW and VDD > Vstb, the circuit is enabled and FDI acts as the input for ringing frequency detection. When FDE is HIGH, the circuit is disabled and FDI becomes the enable/disable input for tone sequence generation. When the circuit is enabled, it starts to produce output ringing tones after one cycle of an appropriate input frequency is detected at FDI. An input cycle is detected when either 2 rising or 2 falling edges are received, and this implies a delay of between 1 and 1.5 input cycles before output ringing begins. The allowed input frequency range is set by the states of pins FL and FH, as shown in Table 2. Output ringing continues for as long as valid input ringing frequency is detected. FDI has a Schmitt-trigger action; the levels are set by an external resistor R2 (see Fig.8) and an internal sink current that is switched from 20 µA (typ.) for FDI = LOW to <0.1 µA for FDI = HIGH. Excess current entering FDI via R2 is absorbed by internal diodes clamped to VDD and VSS. 7.5 Selection of frequency discriminator limits (FL and FH) With the frequency discriminator enabled (VDD > Vstb and FDE = LOW) the lower and upper limits of the input frequency are set by the inputs FL and FH as shown by Table 2. Table 2 Selection of lower and upper frequency discriminator limits (fOSC = 64 kHz) FL INPUT STATE LOWER LIMIT FH INPUT STATE UPPER LIMIT LOW HIGH 20 Hz 13.3 Hz LOW HIGH 60 Hz 30 Hz (1) Transistor resistance is RIL when switched on. Fig.3 Input circuit of selection pins. 1997 Jan 15 5 5 Page Philips Semiconductors Programmable multi-tone telephone ringer Product speciﬁcation PCD3360 10 DC CHARACTERISTICS VDD = 6.0 V; VSS = 0 V; fOSC = 64 kHz; Tamb = −25 to +70 °C; valid enable conditions at FDI and FDE; all voltages with respect to VSS; unless otherwise speciﬁed. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD operating supply voltage Vstb standby supply voltage note 1 VAS supply voltage for automatic note 2 swell reset IDD operating supply current note 3 Istb standby supply current VDD < Vstb; note 4 Inputs VIL LOW level input voltage VIH HIGH level input voltage PULL-DOWN CIRCUIT OF INPUTS FDE, R1, RR2, DM, IS1, IS2, TS1, FL, FH RIL pull-down resistance IIH pull-down current input at VSS input at VDD PULL-DOWN CIRCUIT OF FDI ISL TC(FDI) ISH ISX IIS pull-down current (LOW) temperature coefﬁcient of ISL pull-down current (HIGH) pull-down current (STANDBY) current into input FDI VFDI = 0.3VDD; Tamb = 25 °C VFDI = 0.3VDD; Tamb = 25 °C VFDI = 0.8VDD VDD < Vstb note 5 Outputs, TONE and OPT IOL output sink current IOH output source current VOL = 0.5 V VOL = −0.5 V Vstb + 0.1 − 3.9 4.8 0.5Vstb − 110 −3 0 0.7VDD − − − 20 − 0.1 14 23 − 0.5 − 0.1 − 0.1 −0.2 − 12 −1 −2 8.0 5.7 140 8 0.3VDD VDD − − 32 − − − +0.2 − − V V V µA µA V V kΩ µA µA %/°C µA µA mA mA mA Notes 1. For VDD < Vstb the circuit is in standby mode. 2. At VDD = VAS the automatic swell register is reset. 3. ROSC = 365 kΩ; COSC = 56 pF; FDI = FDE = VDD; all other inputs and outputs open-circuit; see Figs 8 and 9. 4. The standby supply current is measured with all inputs and outputs open-circuit, with the exception of OSC. 5. The current IIS is clamped to VDD and to VSS by two internal diodes. Correct operation is ensured with VFDI > VDD or VFDI < VSS, provided the maximum value of IIS is not exceeded. (The input FDI has an extended HIGH and LOW input voltage range.) 1997 Jan 15 11 11 Page

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