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PDF PCD3352A Data sheet ( Hoja de datos )

Número de pieza PCD3352A
Descripción 8-bit microcontrollers with DTMF generator and 128 bytes EEPROM
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
DATA SHEET
PCA3351C; 52C; 53C;
PCD3351A; 52A; 53A
8-bit microcontrollers with DTMF
generator and 128 bytes EEPROM
Product specification
Supersedes data of 1996 Dec 18
File under Integrated Circuits, IC03
1999 Oct 28

1 page




PCD3352A pdf
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P2.0 to P2.3
4
PORT 2
BUFFER
PORT 2
FLIP-FLOP
4
TONE
FILTER
SINE WAVE
GENERATOR
HGF
REGISTER
LGF
REGISTER
88
MELODY
CONTROL
REGISTER
8
INTERNAL
CLOCK
FREQ.
30
32
T1
P1.7/MDY P1.0 to P1.6
7
PORT 1
BUFFER
PORT 1
FLIP-FLOP
RESIDENT ROM
2 kbytes
(PCD3351C; 51A)
4 kbytes
(PCD3352C; 52A)
6 kbytes
(PCD3353C; 53A)
MEMORY
BANK
FLIP-FLOPS
DECODE
P0.0 to P0.7
8
PORT 0
BUFFER
PORT 0
FLIP-FLOP
TIMER/
EVENT
COUNTER
8
PCA3351C
PCA3352C
PCA3353C
8
PCD3351A
PCD3352A
PCD3353A
HIGHER
PROGRAM
COUNTER
5
LOWER
PROGRAM
COUNTER
PROGRAM
STATUS
WORD
88 8
8
8
88 8 8
8
8
88
88
8
TIMER 2
RELOAD
REGISTER
TIMER 2
REGISTER
EEPROM
CONTROL
REGISTER
EEPROM
ADDRESS
REGISTER
EEPROM
DATA
TRANSFER
INTERRUPT
LOGIC
ACCUMULATOR
TEMPORARY
REGISTER 1
POWER-ON-RESET VPOR
RESET
EEPROM
derivative
interrupt
timer interrupt
external interrupt
TEMPORARY
REGISTER 2
ARITHMETIC
LOGIC UNIT
DECIMAL
ADJUST
STOP
IDLE
CE/T0
CONTROL AND TIMING
RESET
XTAL1
XTAL2
INTERRUPT INITIALIZE
OSCILLATOR
INSTRUCTION
REGISTER
AND
DECODER
RAM
ADDRESS
REGISTER
CONDITIONAL
BRANCH
LOGIC
T1
CE/T0
TIMER
FLAG
CARRY
ACC
ACC BIT
TEST
8
MULTIPLEXER
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
D REGISTER 6
E REGISTER 7
C
O 8 LEVEL STACK
D (VARIABLE LENGTH)
E OPTIONAL SECOND
REGISTER BANK
DATA STORE
RESIDENT RAM ARRAY
64 bytes
(PCD3351C; 51A)
128 bytes
(PCD3352C; 52A; 53C; 53A)
MLA537
Fig.1 Block diagram.

5 Page





PCD3352A arduino
Philips Semiconductors
8-bit microcontrollers with DTMF generator
and 128 bytes EEPROM
Product specification
PCA3351C; 52C; 53C;
PCD3351A; 52A; 53A
6.5 Modem frequencies
Again assuming an oscillator frequency fxtal = 3.58 MHz,
the standard modem frequencies can be implemented as
in Table 9. It is suggested to define the frequency by the
HGF register while the LGF register contains 00H,
disabling Low Group Frequency generation.
Table 9 Standard modem frequencies and their
implementation
HGF
VALUE
(HEX)
FREQUENCY (Hz)
MODEM GENERATED
9D 980(1)
978.82
82 1180(1)
1 179.03
8F 1070(2)
1 073.33
79 1270(2)
1 265.30
80 1200(3)
1 197.17
45 2200(3)
2 192.01
76 1300(4)
1 296.94
48 2100(4)
2 103.14
5C 1650(1)
1 655.66
52 1850(1)
1 852.77
4B 2025(2)
2 021.20
44 2225(2)
2 223.32
DEVIATION
(%) (Hz)
0.12 1.18
0.08 0.97
0.31 3.33
0.37 4.70
0.24 2.83
0.36 7.99
0.24 3.06
0.15 3.14
0.34 5.66
0.15 2.77
0.19 3.80
0.08 1.68
Notes
1. Standard is V.21.
2. Standard is Bell 103.
3. Standard is Bell 202.
4. Standard is V.23.
6.6 Musical scale frequencies
Finally, two octaves of musical scale in steps of semitones
can be realized, again assuming an oscillator frequency
fxtal = 3.58 MHz (Table 10). It is suggested to define the
frequency by the HGF register while the LGF contains
00H, disabling Low Group Frequency generation
Table 10 Musical scale frequencies and their
implementation
NOTE
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
B6
C7
C#7
D7
D#7
HGF
VALUE
(HEX)
F8
EA
DD
D0
C5
B9
AF
A5
9C
93
8A
82
7B
74
6D
67
61
5C
56
51
4D
48
44
40
3D
FREQUENCY (Hz)
STANDARD(1) GENERATED
622.3
659.3
698.5
740.0
784.0
830.6
880.0
923.3
987.8
1 046.5
1 108.7
1 174.7
1 244.5
1 318.5
1 396.9
1 480.0
1 568.0
1 661.2
1 760.0
1 864.7
1 975.5
2 093.0
2 217.5
2 349.3
2 489.0
622.5
659.5
697.9
741.1
782.1
832.3
879.3
931.9
985.0
1 044.5
1 111.7
1 179.0
1 245.1
1 318.9
1 402.1
1 482.2
1 572.0
1 655.7
1 768.5
1 875.1
1 970.0
2 103.3
2 223.3
2 358.1
2 470.4
Note
1. Standard scale based on A4 @ 440 Hz.
1999 Oct 28
11

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