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PDF PCD3311CP Data sheet ( Hoja de datos )
| Número de pieza | PCD3311CP | |
| Descripción | DTMF/modem/musical-tone generators | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
PCD3311C; PCD3312C
DTMF/modem/musical-tone
generators
Product specification
Supersedes data of May 1990
File under Integrated Circuits, IC03
1996 Nov 21
1 page  
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
6.3 Pinning PCD3311CT
handbook, halfpage
OSCI 1
OSCO 2
MODE 3
16 VDD
15 VSS
14 D4
D5 4
13 n.c.
PCD3311CT
n.c. 5
12 D3
STROBE 6
11 D2
TONE 7
10 D1/SDA
A0 8
9 D0/SCL
MGG509
Fig.3 Pin configuration PCD3311CT.
6.5 Pinning PCD3312C
handbook, halfpage
VSS 1
8 SDA
VDD 2
7 SCL
PCD3312C
OSCI 3
6 A0
OSCO 4
5 TONE
MGG510
6.4 Pin description PCD3311CT
SYMBOL PIN TYPE
DESCRIPTION
OSCI
1 I oscillator input
OSCO
2 O oscillator output
MODE
3 I mode select input (selects
I2C or parallel data input)
D5 4 I parallel data input
n.c.
STROBE
5
6
− not connected
I strobe input (for loading
data in parallel mode)
TONE
7 O frequency output (DTMF,
modem, musical tones)
A0
D0/SCL
8
9
I slave address input (to be
connected to VDD or VSS)
I parallel data input or
I2C-bus clock line
D1/SDA 10
I parallel data input or
I2C-bus data line
D2, D3 11, 12 I parallel data inputs
n.c. 13 − not connected
D4 14 I parallel data input
VSS 15 P negative supply
VDD 16 P positive supply
6.6 Pin description PCD3312C
SYMBOL PIN TYPE
DESCRIPTION
VSS
VDD
OSCI
1 P negative supply
2 P positive supply
3 I oscillator input
OSCO
4 O oscillator output
TONE
5 O frequency output (DTMF,
modem, musical tones)
A0
SCL
SDA
6 I slave address input (to be
connected to VDD or VSS)
7 I I2C-bus clock line
8 I I2C-bus data line
Fig.4 Pin configuration PCD3312C.
1996 Nov 21
5
5 Page 
Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
8 I2C-BUS INTERFACE
The I2C-bus is for two-way communication between different ICs or modules. It uses only two lines, a serial data line
(SDA) and a serial clock line (SCL), both of which are bi-directional. Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
8.1 Bit transfer (see Fig.7)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.7 Bit transfer.
8.2 Start and stop conditions (see Fig.8)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SCL
S
START condition
SDA
SCL
P
STOP condition
MBC622
Fig.8 Start and stop conditions.
1996 Nov 21
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet PCD3311CP.PDF ] | |
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