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PDF S2100 Data sheet ( Hoja de datos )
| Número de pieza | S2100 | |
| Descripción | 64-bit FUSE ROM | |
| Fabricantes | Seiko Instruments | |
| Logotipo |  |
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Contents
Features........................................................... 1
Applications...................................................... 1
Pin Assignment ................................................ 1
Block Diagram.................................................. 1
Terminal Description ........................................ 2
Mode Table ...................................................... 2
Absolute Maximum Ratings ............................. 2
Recommended Operating Conditions.............. 2
DC Electrical Characteristics ........................... 3
AC Electrical Characteristics............................ 3
Read Mode Operation...................................... 4
Counter Hold Mode Operation ......................... 4
Program Mode Operation ................................ 5
Input Priority ..................................................... 6
Notes................................................................ 6
Dimensions ...................................................... 7
Characteristics ................................................. 8
1 page  
64-bit FUSE ROM
S-2100R
Read Mode Operation
By setting the CE/PE terminal to “ L” level, the S-2100R enters the read mode. *1 Next, adding an RST pulse causes the
contents of the memory bit of address 1 to be output at the DATA terminal; the rising of the RST pulse latches the data and
stabilizes it. *2 Reading of addresses from 2 to 64 can be done by adding a CLK pulse sequentially after reading address 1. *3
As soon as address 64 has been read, the COUNTER OUT terminal outputs “ H” level. When it finishes reading address 64, it
does not accept any more CLK pulses and the counter does not operate. The data of address 64 is maintained till address 1 is
read by the RST pulse.
CE/PE
RST
CLK
DATA
tCES
tCE
tRH
tRC
tACC
Address 1 output
tCH
tACC
tRC
Address 2 output
tRC
Address 3 output
Figure 3 Read mode timing
tRS
Address 1 output
*1 When both the CLK and RST terminals are at “ H” level.
*2 When the RST terminal is at “ L” level, the latch is transparent and the data is recognized by the rising of the RST pulse.
*3 Data read by the CLK pulse is latched at its rising.
Counter Hold Mode Operation
By setting the CE/PE terminal to “ H” level, the S-2100R enters the counter hold mode and the DATA terminal becomes high
impedance.
*4
In counter hold mode, the CLK and RST pulses which fall while the CE/PE terminal is at “ H” level are recognized to be invalid
and there is no change in counter and data output. When the CE/PE terminal is set to “ L” level again, it returns to the
condition in which it was before the counter hold mode.
CE/PE
RST
CLK
tCRI
DATA
Address M
output
tCES
tCS
tWZ
Address M+1 output
Figure 4 Counter hold mode timing
Address M+1 output
*4 When both the CLK and RST terminals are at “ H” level.
4 Seiko Instruments Inc.
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet S2100.PDF ] | |
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