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PDF S1M8836X01-G0T0 Data sheet ( Hoja de datos )

Número de pieza S1M8836X01-G0T0
Descripción FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Fabricantes Samsung semiconductor 
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
INTRODUCTION
24-QFN-3.5×4.5
The S1M8836/37 is a Fractional-N frequency synthesizer with integrated
prescalers, designed for RF operation up to 1.0GHz/2.5GHz and for IF
operation up to 520MHz. The fractional-N synthesizer allows fast-locking, low
phase noise phase-locked loops to be built easily, thus having rapid channel
switching and reducing standby time for extended battery life. The S1M8836/37
based on Σ - fractional-N techniques solves the fractional spur problems in
other fractional-N synthesizers based on charge pump compensation. The
synthesizer also has an additional feature that the PCS/CDMA channel
frequency in steps of 10kHz can be accurately programmed.
The S1M8836/37 contains quadruple-modulus prescalers. The S1M8836 RF
synthesizer adopts an 8/9/12/13 prescaler(16/17/20/21 for the S1M8837) and the IF synthesizer adopts an 8/9
prescaler. Phase detector gain is user-programmable for maximum flexibility to address IS-95 CDMA and
IMT2000. Various program-controlled power down options as well as low supply voltage help the design of
wireless cell phones having minimum power consumption.
Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8836/37 has a linear phase
detector characteristic and can be used for very stable, low noise PLL's. Supply voltage can range from 2.7V to
4.0V. The S1M8836/37 is available in a 24-QFN package.
FEATURES
High operating frequency dual synthesizer
Operating voltage range : 2.7 to 4.0V
Low current consumption(S1M8836: 5.5mA, S1M8837: 7.5mA)
Selectable power saving mode (Icc = 1uA typical @3V)
Quadruple-modulus prescaler and Fractional-N/Integer-N:
S1M8836
(RF) 8/9/12/13
Fractional-N
S1M8837
(RF) 16/17/20/21 Fractional-N
S1M8836/37
(IF) 8/9
Integer-N
S1M8836: 250MHz to 1.0GHz(RF) / 45MHz to 520MHz(IF)
S1M8837: 500MHz to 2.5GHz(RF) / 45MHz to 520MHz(IF)
Excellent in-band phase noise ( – 85dBc/Hz @ PCS, – 90dBc/Hz @ CDMA)
Improved fractional spurious performance ( < 80dBc )
Frequency resolution (= 10kHz/64 @ fref = 9.84MHz)
Fast channel switching time: <500us
Programmable charge pump output current: from 50µA to 800µA in 50µA steps
Programmability via on-chip serial bus interface
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S1M8836X01-G0T0 pdf
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PIN DESCRIPTION
Pin No. Symbol I/O
Descriptions
1 VDDRF – RF PLL power supply (2.7V to 4.0V). Must be equal to VDDIF.
2 VpRF – Power supply for RF charge pump. Must be VDDRF and VDDIF.
3 CPoRF O RF charge pump output. Connected to an external loop filter.
4 DGND – Ground for RF PLL digital circuitry.
5 finRF I RF prescaler input. Small signal input from the external VCO.
I RF prescaler complementary input. For a single-ended output RF VCO, a bypass
6 finRF
capacitor should be placed as close as possible to this pin and be connected
directly to the ground plane.
7 GNDRF – Ground for RF PLL analog circuitry.
8 VDDRFa – PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to VDDRF
9 OSCin I Oscillator input to drive both the IF and RF R counter inputs.
10 foLD O Multiplexed output of N or R divider and RF/IF lock detect.
11 RF_EN I RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL
to power down directly, not depending on a program control. Also sets the charge
pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on
the state of RF_CTL_WORD.
12 IF_EN I IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL
to power down directly. The same as RF_EN except that power-up depends on the
state of IF_CTL_WORD.
13 CLOCK I CMOS clock input. Data for the various counters is clocked into the 22-bit shift
register on the rising edge.
14 DATA I Binary serial data input. Data entered MSB (Most Significant Bit) first.
15 LE I Load enable when LE goes HIGH. High impedance CMOS input.
16 GNDIF – Ground for IF analog circuitry.
17 finIF I IF prescaler complementary input. For a single-ended output IF VCO, a bypass
capacitor should be placed as close as possible to this pin.
18 finIF I IF prescaler input. Small signal input from the VCO.
19 DGND – Ground for IF PLL digital circuitry.
20 CPoIF O IF charge pump output. Connected to an external loop filter.
21 VpIF – Power supply for IF charge pump. Must be VDDRF and VDDIF.
22 VDDIF – IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF.
23 OUT1 O Programmable CMOS output. Level of the output is controlled by W2[19] bit.
24 OUT0 O Programmable CMOS output. Level of the output is controlled by W2[18] bit.
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous
switches between active low and tri-state.
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S1M8836X01-G0T0 arduino
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
FUNCTIONAL DESCRIPTION
S1M8836/37
finRF
finRF
+
-
CLOCK
DATA
LE
RF
Prescaler
RF
N Counter
-
Modulator
Serial Data Control
RF
R Counter
OSC in
finIF +
finIF -
IF
R Counter
IF
Prescaler
IF
N Counter
RF
Phase
Detector
RF
Charge
Pump
RF
LD
CMOS
Output
MUX
foLD
Data Out
Multiplexer
CMOS
Output
MUX
IF
LD
IF
Phase
Detector
IF
Charge
Pump
CP oRF
OUT0
foLD
OUT1
CP oIF
The Samsung S1M8836/37 is RF/IF dual frequency synthesizer IC which supports Fractional-N mode for RF PLL
and Integer-N mode for IF PLL depending on a program control. S1M8836/37 combined with an external LPF and
an external VCO forms PLL frequency synthesizer. The frequency synthesizer consists of prescalers, pulse-
swallowed programmable N counters, programmable reference R counters, phase detectors, programmable
charge pumps, analog LD(lock detector), serial data control, etc.
An input buffer in the prescaler amplifies the RF input power of -10dBm from the external RF/IF VCO to the
sufficient ECL switching level to drive the following ECL divider so that it can be normally operated even in a
smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a pre-
determined divide ratio (div. 8/9/12/13 for S1M8836, div. 16/17/20/21 for S1M8837, div. 8/9 for IF), the N counter
and the Fractional-N circuitry( Σ - modulator). External reference signal is divided by the R counter to set the
comparison frequency of the PFD. The divide ratios of the programmable counters can be programmed via the
serial bus interface. These two signals drive the both inputs of the phase detector. The phase detector drives the
charge pump by comparing frequencies and phases of the above two signals. The charge pump and the external
LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency
signal.
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