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PDF S1M8656A01-E0T0 Data sheet ( Hoja de datos )

Número de pieza S1M8656A01-E0T0
Descripción CDMA/AMPS Dual Mode IF/ baseband IC
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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RX IF/BBA WITH AGC
INTRODUCTION
S1M8656A/8657 are CDMA/AMPS Dual Mode IF/ baseband IC which is
divided into three main parts - IF frequency processing, basband
processing , and digital interface. The receiver IC (S1M8656A)and
transmitter IC (S1M8657) are provided as a KIT.
S1M8656A is a receiver IC, installed with a Rx AGC, Baseband
Converter, Baseband analog filter, and A-D Converter. It can send a
digital baseband signal to the digital baseband IC. The S1M8657X01 is a
transmission-only IC, installed with a Tx AGC, IF frequency converter,
analog filter, D-A Converter, PLL, 8-bit A-D Converter for the system
monitor, and 3-input analog switch. It connects the digital baseband IC to
the RF processing. Designed to operate in direction connection with the
MSM, S1M8656A and S1M8657 are fabricated on the Samsung's 0.5um
high-speed, high-frequency BICMOS processing and can achieve
superior high frequency and low power digital operations.
Its operating voltage is 2.7V – 3.6V, and operating temperature
-30°C – +85°C .
48-LQFP-0707
48-BCC-7.0×7.0
S1M8656A
FEATURES
CDMA/AMPS Dual Mode
AGC input signal range : 90dB
QPSK Baseband Converter
Built-in I ,Q Baseband signal extractor LPF
Built-in 4-bit ADC for converting I and Q CDMA analog baseband signals to digital baseband signals
Built-in 8-bit ADC for converting I and Q FM analog baseband signals to digital baseband signals
Adopts the Rx SLOT function to minimize the AMPS Mode consumption power
Built-in VCO for baseband conversion
Built-in Modem PDM control circuit to compensate the I and Q offsets
3-Line Serial Port Interface (SPI)
ORDERING INFORMATION
Device
+ S1M8656A01-E0T0
+ S1M8656A01-F0T0
+ : New product
Package
48-LQFP-0707
48-BCC-7.0×7.0
Operating Temperature
-30 to +85°C
1

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S1M8656A01-E0T0 pdf
RX IF/BBA WITH AGC
S1M8656A
PIN DESCRIPTION (Continued)
Pin No
Symbol
I/O
Description
32 SLEEPB/CLK
DI When SEN is high, this pin inputs the clock with the permit of the 3-
line serial control input. When SEN is low, parallel control input is
allowed and this pin performs SLEEPB. If this pin is opened, it
remains at Low.
36 TCXO
AI Reference frequency input terminal connected to the VCTCXO output.
When this pin stops, only DC bias is delivered to maintain the DC
charge value of the capacitor connected externally.
37 TCXO/N
DO Division output of the TCXO Reference frequency input. 3-different
division ratio and 2- output drive capacities can be selected through
the SPI bus control. Default : 4.92MHz, Weak OUT *division ratio : 1,
1/4, 1/16
38 CHIPx8
BI CHIPx8 CLOCK output terminal. It has a division ratio of 512/1025 for
the TCXO reference frequency.
Therefore, it cannot have a perfect 50% duty. When this terminal is
not used (CDMA SLEEP, FM IDLE), it remains at Low. This pin can
be used exclusively for the externally generated CHIPx8 CLOCK input
using the SPI BUS control.
39 RXQD3
DO CDMA A-D Converter's digital outputs, which are connected to the
40 RXQD2
modem data input pins. These data are synchronized at CHIPx8's
41 RXQD1
rising edge and output. Because they are valid at the falling edge, the
42 RXQD0
data are latched at the falling edge in the modem.
45 RXID3
Because the number of 48-pins are restricted in this product, pins 47
46 RXID2
and 48 are shared with the FMDATA pin.
47 RXID1/FMRID
48 RXID0/FMRQD
4, 6,
14,
15, 17,
20, 24
VCC
AI Power input terminal for the analog circuit.
35 VDD
DI Power for the digital logic.
44 VDD
DI Power source for a logic circuit ,related to the digital input /output,
connected to an external digital logic such as the modem.
3, 5, 8,
13, 16,
18, 19,
23, 43
GNDA
AI Analog circuit ground.
Pin-18 is N.C. in the product.
34 GNDD
DI Digital logic circuit ground.
33 NC
- This pin is used for internal testing only and is not connected to
anything.
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S1M8656A01-E0T0 arduino
RX IF/BBA WITH AGC
TIMING DIAGRAMS
CHIPx8 Period: 101.7 ns
High time:
High time:
50.86 +10ns
50.86 +10 ns
CHIPx8
Data hold after CHIPx8
fall > 15ns
Rising time:
3 - 12ns
RDO-3
> 20ns
Valid data
Valid data
Data output stable prior
to CHIPx8 : > 20ns
Falling time:
3 - 12 ns
90%
10%
Valid data
Figure1. CDMA Receive ADC Timing
S1M8656A
FMCLK
Clock period:
2.78us High time:
1.39us
Rising time:
3 - 12ns
10%
Falling time:
3 -12ns
90%
Low time:
1.39us
FMSTB
Strobe pulse width:
1 - 2.78us
Strobe input valid
to clock falling
edge: > 50ns
FMRXDATA
output delay after
clock falling edge: <50ns
Invalid D7 D6 D5 D4 D3 D2 D1 D0
Strobe input valid
after clock falling
edge: > 50ns
* All timing specifications is based on Cload = 12pF, FMCLK=360kHz, FMSTB=40kHz.
Figure 2. FM Receive ADC Timing
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