DataSheet.es    


PDF PCA9564 Data sheet ( Hoja de datos )

Número de pieza PCA9564
Descripción Parallel bus to I2C-bus controller
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



Hay una vista previa y un enlace de descarga de PCA9564 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! PCA9564 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
PCA9564
Parallel bus to I2C-bus controller
Product data
Supersedes data of 2003 Feb 26
2003 Apr 02
Philips
Semiconductors

1 page




PCA9564 pdf
Philips Semiconductors
Parallel bus to I2C-bus controller
Product data
PCA9564
FUNCTIONAL DESCRIPTION
General
The PCA9564 acts as an interface device between standard
high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it
can act either as master or slave. Bidirectional data transfer between
the I2C-bus and the parallel-bus microcontroller is carried out on a
byte-wise basis, using either an interrupt or polled handshake.
Internal Oscillator
The PCA9564 contains an internal 9 MHz oscillator which is used
for all I2C timing. The oscillator requires up to 500 µs to start-up
after ENSIO bit is set to 1.
Registers
The PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
The registers are selected by setting pins A0 and A1 to the
appropriate logic levels before a read or write operation is executed.
CAUTION: Do not write to I2C registers while the I2C-bus is busy
and the SIO is in master or addressed slave mode.
REGISTER REGISTER
NAME FUNCTION
I2CSTA
Status
I2CTO
Time-out
I2CDAT
Data
I2CADR Own address
I2CCON
Control
A1
0
0
0
1
1
A0
READ/
WRITE
0R
0W
1 R/W
0 R/W
1 R/W
DEFAULT
F8h
FFh
00h
00h
00h
The Time-out Register, I2CTO: The time-out register is used to
determine the maximum time that SCL is allowed to be LOW before
the I2C state machine is reset.
When the I2C interface is operating, I2CTO is loaded in the time-out
counter at every SCL transition.
I2CTO
76
TE TO6
5
TO5
432
TO4 TO3 TO2
10
TO1 TO0
Time-out value
The most significant bit of I2CTO (TE) is used as a time-out
enable/disable. A 1will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1) × 113.7 µs. The time-out value may vary
some and is an approximate value.
The time-out register can be used in the following cases:
1. When the SIO, in the master mode, wants to send a START
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO.
2. In the master mode, the time-out feature starts every time the SCL
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
3. In case of a forced access to the I2C-bus. (See more details on
page 15.)
The Address Register, I2CADR: I2CADR is not affected by the
SIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontrollers own slave address.
76
5
432 1 0
I2CADR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 0
own slave address
The most significant bit corresponds to the first bit received from the
I2C-bus after a start condition. A logic 1 in I2CADR corresponds to a
HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW
level on the bus. The least significant bit is not used but should be
programmed with a 0.
The Data Register, I2CDAT: I2CDAT contains a byte of serial data
to be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
out on the I2C-bus, with the most significant bit of the slave address
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
transferred on the I2C-bus.
NOTE: The I2CDAT register will capture the serial address as data
when addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
765 43 2 1 0
I2CDAT
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
corresponds to a HIGH level on the I2C-bus, and a logic 0
corresponds to a LOW level on the bus.
The Control Register, I2CCON: The microcontroller can read from
and write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the
I2C-bus.
7 6 5 4 32 1 0
I2CCON
AA ENSIO STA STO SI CR2 CR1 CR0
ENSIO, THE SIO ENABLE BIT
ENSIO = 0: When ENSIO is 0, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the not addressedslave state.
ENSIO = 1: When ENSIO is 1, SIO is enabled.
After the ENSIO bit is set, it takes 500 µs for the internal oscillator to
start up, therefore, the PCA9564 will enter either the master or the
slave mode after this time. ENSIO should not be used to temporarily
release the PCA9564 from the I2C-bus since, when ENSIO is reset,
the I2C-bus status is lost. The AA flag should be used instead (see
description of the AA flag in the following text).
In the following text, it is assumed that ENSIO = 1.
STA, THE START FLAG
2003 Apr 02
5

5 Page





PCA9564 arduino
Philips Semiconductors
Parallel bus to I2C-bus controller
Product data
PCA9564
Table 2. Master Transmitter Mode
STATUS
CODE
(I2CSTA)
STATUS OF THE
I2C BUS AND
SIO HARDWARE
APPLICATION SOFTWARE RESPONSE
TO/FROM I2CDAT
TO I2CCON
STA STO SI AA
NEXT ACTION TAKEN BY SIO HARDWARE
08H A START condition has Load SLA+W
been transmitted
10H A repeated START
condition has been
transmitted
Load SLA+W or
Load SLA+R
X X 0 X SLA+W will be transmitted;
ACK bit will be received
X X 0 X As above
X X 0 X SLA+R will be transmitted;
SIO will be switched to MST/REC mode
18H SLA+W has been
transmitted; ACK has
been received
Load data byte or
no I2CDAT action or
no I2CDAT action or
no I2CDAT action
0
1
0
1
0 0 X Data byte will be transmitted;
ACK bit will be received
0 0 X Repeated START will be transmitted;
1 0 X STOP condition will be transmitted;
STO flag will be reset
1 0 X STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
20H SLA+W has been
Load data byte or
0
transmitted; NOT ACK
has been received
no I2CDAT action or 1
no I2CDAT action or 0
no I2CDAT action
1
0 0 X Data byte will be transmitted;
ACK bit will be received
0 0 X Repeated START will be transmitted;
1 0 X STOP condition will be transmitted;
STO flag will be reset
1 0 X STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
28H Data byte in I2CDAT
Load data byte or
0
has been transmitted;
ACK has been received no I2CDAT action or 1
no I2CDAT action or 0
no I2CDAT action
1
0 0 X Data byte will be transmitted;
ACK bit will be received
0 0 X Repeated START will be transmitted;
1 0 X STOP condition will be transmitted;
STO flag will be reset
1 0 X STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
30H Data byte in I2CDAT
has been transmitted;
NOT ACK has been
received
Load data byte or
no I2CDAT action or
no I2CDAT action or
no I2CDAT action
0
1
0
1
0 0 X Data byte will be transmitted;
ACK bit will be received
0 0 X Repeated START will be transmitted;
1 0 X STOP condition will be transmitted;
STO flag will be reset
1 0 X STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
38H Arbitration lost in
SLA+W or
Data bytes
No I2CDAT action or 0 0 0 X I2C-bus will be released;
not addressed slave will be entered
No I2CDAT action
1 0 0 X A START condition will be transmitted when the
bus becomes free (STOP or SCL and SDA high)
2003 Apr 02
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet PCA9564.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
PCA9560Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switchNXP Semiconductors
NXP Semiconductors
PCA9561Quad 6-bit multiplexed I2C EEPROM DIP switchNXP Semiconductors
NXP Semiconductors
PCA9564Parallel bus to I2C-bus controllerNXP Semiconductors
NXP Semiconductors
PCA9564BSParallel bus to I2C-bus controllerNXP Semiconductors
NXP Semiconductors

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar