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PDF PCA9554ATS Datasheet ( Hoja de datos )

Número de pieza PCA9554ATS
Descripción 8-bit I2C and SMBus I/O port with interrupt
Fabricantes NXP 
Logotipo NXP Logotipo

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PCA9554ATS Hoja de datos, Descripción, Manual
INTEGRATED CIRCUITS
PCA9554/PCA9554A
8-bit I2C and SMBus I/O port with interrupt
Product data sheet
Supersedes data of 2002 Jul 26
2004 Sep 30
Philips
Semiconductors

1 page

PCA9554ATS pdf
Philips Semiconductors
8-bit I2C and SMBus I/O port with interrupt
Product data sheet
PCA9554/PCA9554A
REGISTERS
Command Byte
Command
Protocol
Function
0
Read byte
Input port register
1 Read/write byte Output port register
2 Read/write byte Polarity inversion register
3 Read/write byte Configuration register
The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 0 – Input Port Register
bit I7 I6 I5 I4 I3 I2 I1 I0
default X X X X X X X X
This register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic
level, normally ‘1’ when no external signal externally applied
because of the internal pull-up resistors.
Register 1 – Output Port Register
bit O7 O6 O5 O4 O3 O2 O1 O0
default 1 1 1 1 1 1 1 1
This register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.
Register 2 – Polarity Inversion Register
bit N7 N6 N5 N4 N3 N2 N1 N0
default 0 0 0 0 0 0 0 0
This register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with ‘1’), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a ‘0’), the Input Port data polarity is retained.
Register 3 – Configuration Register
bit C7 C6 C5 C4 C3 C2 C1 C0
default 1 1 1 1 1 1 1 1
This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high-impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to VDD.
Power-on Reset
When power is applied to VDD, an internal power-on reset holds the
PCA9554 in a reset condition until VDD has reached VPOR. At that
point, the reset condition is released and the PCA9554 registers and
state machine will initialize to their default states. Thereafter, VDD
must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then
restored to the operating voltage.
Interrupt Output
The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the input port register.
2004 Sep 30
5

5 Page

PCA9554ATS arduino
Philips Semiconductors
8-bit I2C and SMBus I/O port with interrupt
Product data sheet
PCA9554/PCA9554A
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.
DC CHARACTERISTICS
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP
MAX
Supplies
VDD Supply voltage
IDD Supply current
Istbl Standby current
Istbh Standby current
VPOR Power-on reset voltage (Note 1)
Input SCL; input/output SDA
Operating mode; VDD = 5.5 V; no load;
fSCL = 100 kHz
Standby mode; VDD = 5.5 V; no load;
VI = VSS; fSCL = 0 kHz; I/O = inputs
Standby mode; VDD = 5.5 V; no load;
VI = VDD; fSCL = 0 kHz; I/O = inputs
No load; VI = VDD or VSS
2.3
104
550
0.25
1.5
5.5
175
700
1
1.65
VIL
VIH
IOL
IL
CI
I/Os
LOW level input voltage
HIGH level input voltage
LOW level output current
Leakage current
Input capacitance
VOL = 0.4 V
VI = VDD = VSS
VI = VSS
–0.5
0.7VDD
3
–1
6
0.3VDD
5.5
+1
10
VIL LOW level input voltage
VIH HIGH level input voltage
IOL LOW level output current
VOH HIGH level output voltage
IIH Input leakage current
IIL Input leakage current
CI Input capacitance
CO Output capacitance
Interrupt INT
VOL = 0.5 V; VDD = 2.3 V; Note 2
VOL = 0.7 V; VDD = 2.3 V; Note 2
VOL = 0.5 V; VDD = 4.5 V; Note 2
VOL = 0.7 V; VDD = 4.5 V; Note 2
VOL = 0.5 V; VDD = 3.0 V; Note 2
VOL = 0.7 V; VDD = 3.0 V; Note 2
IOH = –8 mA; VDD = 2.3 V; Note 3
IOH = –10 mA; VDD = 2.3 V; Note 3
IOH = –8 mA; VDD = 3.0 V; Note 3
IOH = –10 mA; VDD = 3.0 V; Note 3
IOH = –8 mA; VDD = 4.75 V; Note 3
IOH = –10 mA; VDD = 4.75 V; Note 3
VDD = 3.6 V; VI = VDD
VDD = 5.5 V; VI = VSS
–0.5 —
2.0 —
8 10
10 13
8 17
10 24
8 14
10 19
1.8 —
1.7 —
2.6 —
2.5 —
4.1 —
4.0 —
——
——
— 3.7
— 3.7
0.8
5.5
1
–100
5
5
IOL LOW level output current
Select Inputs A0, A1, A2
VOL = 0.4 V
3—
VIL LOW level input voltage
–0.5 —
0.8
VIH HIGH level input voltage
2.0 —
5.5
ILI Input leakage current
–1 —
1
NOTES:
1. VDD must be lowered to 0.2 V in order to reset part.
2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
3. The total current sourced by all I/Os must be limited to 85 mA.
UNIT
V
µA
µA
µA
V
V
V
mA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
µA
µA
pF
pF
mA
V
V
µA
2004 Sep 30
11

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