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PDF PCA9548 Data sheet ( Hoja de datos )

Número de pieza PCA9548
Descripción 8-channel I2C switch with reset
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No Preview Available ! PCA9548 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
PCA9548
8-channel I2C switch with reset
Product data sheet
Supersedes data of 2002 Feb 19
2004 Sep 30
Philips
Semiconductors

1 page




PCA9548 pdf
Philips Semiconductors
8-channel I2C switch with reset
Product data sheet
PCA9548
DEVICE ADDRESSING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9548 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
1 1 1 0 A2 A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW00915
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9548, which will be stored
in the control register. If multiple bytes are received by the
PCA9548, it will save the last byte received. This register can be
written and read via the I2C-bus.
CHANNEL SELECTION BITS
(READ/WRITE)
76 5 43 21 0
B7 B6 B5 B4 B3 B2 B1 B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
SW00932
Figure 4. Control register
CONTROL REGISTER DEFINITION
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9548 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I2C-bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
B7 B6 B5 B4 B3 B2 B1 B0 COMMAND
0
Channel 0
disabled
XXXXXXX
1
Channel 0
enabled
0
Channel 1
disabled
XXXXXX
X
1
Channel 1
enabled
0
Channel 2
disabled
XXXXX
XX
1
Channel 2
enabled
0
Channel 3
disabled
XXXX
XXX
1
Channel 3
enabled
0
Channel 4
disabled
XXX
XXXX
1
Channel 4
enabled
0
Channel 5
disabled
XX
XXXXX
1
Channel 5
enabled
0
Channel 6
disabled
X XXXXXX
1
Channel 6
enabled
0
Channel 7
disabled
XXXXXXX
1
Channel 7
enabled
No channel
0
0
0
0
0
0
0
0
selected;
power-up/reset
default state
NOTE: Several channels can be enabled at the same time.
Ex: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0,
means that channels 7, 5, 4, 1, and 0 are disabled and channels 6,
3, and 2 are enabled.
Care should be taken not to exceed the maximum bus capacitance.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of tWL, the PCA9548 will reset its registers and I2C state
machine and will deselect all channels. The RESET input must be
connected to VDD through a pull-up resistor.
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds
the PCA9548 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9548 registers and
I2C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
2004 Sep 30
5

5 Page





PCA9548 arduino
Philips Semiconductors
8-channel I2C switch with reset
Product data sheet
PCA9548
DC CHARACTERISTICS
VDD = 3.6 V to 5.5 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified. (See page 10 for VDD = 2.3 V to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN TYP MAX
Supply
VDD Supply voltage
IDD Supply current
Istb Standby current
VPOR
Power-on reset voltage
Input SCL; input/output SDA
Operating mode; VDD = 5.5 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
Standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
no load; VI = VDD or VSS
3.6 — 5.5
— 575 600
— 250 300
— 1.7 2.1
VIL LOW-level input voltage
VIH HIGH-level input voltage
IOL LOW-level output current
IIL LOW-level input current
IIH HIGH–level input current
Ci Input capacitance
Select inputs A0 to A2 / RESET
VOL = 0.4 V
VOL = 0.6 V
VI = VSS
VI = VDD
VI = VSS
–0.5
— 0.3VDD
0.7VDD
6
3 ——
6 ——
–10 — +10
— — 100
— 20 21
VIL
VIH
ILI
Ci
Pass Gate
LOW-level input voltage
HIGH-level input voltage
Input leakage current
Input capacitance
pin at VDD or VSS
VI = VSS
–0.5
0.7VDD
–1
— +0.3VDD
— VDD + 0.5
— +50
25
RON
Switch resistance
VCC = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA
4
11 24
VPass
Switch output voltage
Vswin = VDD = 5.0 V; Iswout = –100 µA
— 3.5 —
Vswin = VDD = 4.5 V to 5.5 V; Iswout = –100 µA
2.6
4.5
IL Leakage current
VI = VDD or VSS
–10 — +10
Cio Input/output capacitance
VI = VSS
—3 5
UNIT
V
µA
µA
V
V
V
mA
mA
µA
µA
pF
V
V
µA
pF
V
V
µA
pF
2004 Sep 30
11

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