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PDF PCA9545PW Data sheet ( Hoja de datos )

Número de pieza PCA9545PW
Descripción 4-channel I2C switch with interrupt logic and reset
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
PCA9545
4-channel I2C switch with interrupt logic
and reset
Product data
Supersedes data of 2001 Nov 08
2002 Mar 28
Philips
Semiconductors

1 page




PCA9545PW pdf
Philips Semiconductors
4-channel I2C switch with interrupt logic and reset
Product data
PCA9545
INTERRUPT HANDLING
The PCA9545 provides 4 interrupt inputs, one for each channel, and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9545 and the interrupt output
will be driven LOW. The channel does not need to be active for
detection of the interrupt. A bit is also set in the control register.
Bits 4 – 7 of the control register correspond to channels 0 – 3 of the
PCA9545, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9545 and read the contents of the control
register to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9545 to select this
channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to VDD through a
pull-up resistor.
Table 2. Control Register Read — Interrupt
INT3 INT2 INT1 INT0 B3 B2 B1 B0 COMMAND
0
No interrupt
on channel 0
XXX
XXXX
1
Interrupt on
channel 0
0
No interrupt
on channel 1
XX
XXXXX
1
Interrupt on
channel 1
0
No interrupt
on channel 2
X XXXXXX
1
Interrupt on
channel 2
0
No interrupt
on channel 3
XXXXXXX
1
Interrupt on
channel 3
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of tWL, the PCA9545 will reset its registers and I2C state
machine and will deselect all channels. The RESET input must be
connected to VDD through a pull-up resistor.
POWER-ON RESET
When power is applied to VDD, an internal Power On Reset holds
the PCA9545 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9545 registers and
I2C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9545 are constructed such that
the VDD voltage can be used to limit the maximum voltage that will
be passed from one I2C bus to another.
5.0
4.5
4.0
3.5
Vpass
3.0
2.5
2.0
1.5
1.0
2.0
Vpass vs. VDD
MAXIMUM
TYPICAL
2.5 3.0 3.5 4.0
VDD
MINIMUM
4.5 5.0 5.5
SW00820
Figure 5. Vpass voltage vs. VDD
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9545 to act as a voltage translator, the Vpass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then Vpass should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that Vpass (max.) will be at 2.7 V when the
PCA9545 supply voltage is 3.5 V or lower so the PCA9545 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262 PCA954X
family of I2C/SMBus multiplexers and switches.
2002 Mar 28
5 853-2302 27311

5 Page





PCA9545PW arduino
Philips Semiconductors
4-channel I2C switch with interrupt logic and reset
Product data
PCA9545
AC CHARACTERISTICS
SYMBOL
PARAMETER
tpd
fSCL
tBUF
tHD;STA
Propagation delay from SDA to SDn or SCL to SCn
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
STANDARD-MODE
I2C-BUS
MIN MAX
— 0.31
0 100
4.7 —
4.0 —
FAST-MODE I2C-BUS
MIN MAX
— 0.31
0 400
1.3 —
0.6 —
UNIT
ns
kHz
µs
µs
tLOW
tHIGH
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tR
tF
Cb
tSP
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
4.7 — 1.3 —
4.0 — 0.6 —
4.7 — 0.6 —
4.0 — 0.6 —
02 3.45 02 0.9
250 — 100 —
1000
20 + 0.1Cb3
300
300
20 + 0.1Cb3
300
— 400 — 400
— 50 — 50
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
tVD:DATL
tVD:DATH
tVD:ACK
INT
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
— 1 — 1 µs
— 0.6 — 0.6 µs
— 1 — 1 µs
tiv
tir
Lpwr
Hpwr
RESET
INTn to INT active valid time
INTn to INT inactive delay time
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
— 4 — 4 µs
— 2 — 2 µs
1 — 1 — µs
0.5 — 0.5 — µs
tWL(rst) Pulse width low reset
4 — 4 — ns
trst Reset time (SDA clear)
500 — 500 —
ns
tREC:STA Recovery to Start
0 — 0 — ns
NOTES:
1. Pass gate propagation delay is calculated from the 20 typical RON and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
SCL
P
tHD;STA
S tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
2002 Mar 28
Figure 13. Definition of timing on the I2C-bus
11
tSP
tSU;STO
P
SU00645
853-2302 27311

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