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PDF PCA9543D Data sheet ( Hoja de datos )
| Número de pieza | PCA9543D | |
| Descripción | 2-channel I2C switch with interrupt logic and reset | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
PCA9543
2-channel I2C switch with interrupt logic
and reset
Product data sheet
Supersedes data of 2002 Feb 19
2004 Oct 01
Philips
Semiconductors
1 page  
Philips Semiconductors
2-channel I2C switch with interrupt logic and reset
Product data sheet
PCA9543
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9543 are constructed such that
the VDD voltage can be used to limit the maximum voltage that will
be passed from one I2C-bus to another.
5.0
4.5
4.0
3.5
Vpass
3.0
2.5
2.0
1.5
1.0
2.0
Vpass vs. VDD
MAXIMUM
TYPICAL
2.5 3.0 3.5 4.0
VDD
MINIMUM
4.5 5.0 5.5
SW00820
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9543 to act as a voltage translator, the Vpass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then Vpass should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that Vpass (max.) will be at 2.7 V when the
PCA9543 supply voltage is 3.5 V or lower so the PCA9543 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
More Information can be found in Application Note AN262 PCA954X
family of I2C/SMBus multiplexers and switches.
Figure 5. Vpass voltage
2004 Oct 01
5
5 Page 
Philips Semiconductors
2-channel I2C switch with interrupt logic and reset
Product data sheet
PCA9543
AC CHARACTERISTICS
SYMBOL
PARAMETER
tpd
fSCL
tBUF
tHD;STA
Propagation delay from SDA to SDn or SCL to SCn
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
STANDARD-MODE
I2C-BUS
MIN MAX
— 0.31
0 100
4.7 —
4.0 —
FAST-MODE
I2C-BUS
MIN MAX
— 0.31
0 400
1.3 —
0.6 —
UNIT
ns
kHz
µs
µs
tLOW
tHIGH
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tR
tF
Cb
tSP
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Setup time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
4.7 — 1.3 — µs
4.0 — 0.6 — µs
4.7 — 0.6 — µs
4.0 — 0.6 — µs
02 3.45 02 0.9 µs
250 — 100 — ns
—
1000
20 + 0.1Cb3
300
ns
—
300
20 + 0.1Cb3
300
µs
— 400 — 400 µs
— 50 — 50 ns
tVD:DATL
tVD:DATH
tVD:ACK
INT
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
— 1 — 1 µs
— 0.6 — 0.6 µs
— 1 — 1 µs
tiv
tir
Lpwr
Hpwr
RESET
INTn to INT active valid time
INTn to INT inactive delay time
LOW-level pulse width rejection or INTn inputs
HIGH-level pulse width rejection or INTn inputs
— 4 — 4 µs
— 2 — 2 µs
1 — 1 — ns
500 — 500 — ns
tWL(rst)
Pulse width LOW reset
4 — 4 — ns
trst Reset time (SDA clear)
500 — 500 — ns
tREC:STA Recovery to Start
0 — 0 — ns
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
SCL
P
tHD;STA
S tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
2004 Oct 01
Figure 13. Definition of timing on the I2C-bus
11
tSP
tSU;STO
P
SU00645
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PCA9543D.PDF ] | |
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