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PDF PCA9536 Data sheet ( Hoja de datos )

Número de pieza PCA9536
Descripción 4-bit I2C and SMBus I/O port
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCA9536 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
PCA9536
4-bit I2C and SMBus I/O port
Objective data sheet
2004 Aug 20
Philips
Semiconductors

1 page




PCA9536 pdf
Philips Semiconductors
4-bit I2C and SMBus I/O port
Objective data sheet
PCA9536
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O3
DATA FROM
SHIFT REGISTER
DATA FROM
SHIFT REGISTER
WRITE
CONFIGURATION
PULSE
WRITE PULSE
CONFIGURATION
REGISTER
DQ
FF
CK Q
DQ
FF
CK Q
OUTPUT
PORT
REGISTER
READ PULSE
Q1
INPUT PORT
REGISTER
DQ
FF
CK Q
100 k
Q2
OUTPUT PORT
REGISTER DATA
VDD
ESD PROTECTION DIODE
I/O0 TO I/O3
ESD PROTECTION DIODE
VSS
INPUT PORT
REGISTER DATA
DATA FROM
SHIFT REGISTER
WRITE
POLARITY
PULSE
DQ
FF
CK Q
POLARITY
INVERSION
REGISTER
NOTE: At Power-on Reset, all registers return to default values.
Figure 3. Simplified schematic of I/O0 to I/O3
POLARITY
REGISTER DATA
SW02192
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input with a weak pull-up (100 ktyp.) to VDD. The
input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and
either VDD or VSS.
2004 Aug 20
5

5 Page





PCA9536 arduino
Philips Semiconductors
4-bit I2C and SMBus I/O port
Objective data sheet
PCA9536
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I2C-bus
MIN MAX
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tF
tR
tSP
Operating frequency
Bus free time between STOP and START conditions
Hold time after (repeated) START condition
Repeated START condition setup time
Setup time for STOP condition
Data in hold time
Valid time for ACK condition2
Data out valid time3
Data setup time
Clock LOW period
Clock HIGH period
Clock/Data fall time
Clock/Data rise time
Pulse width of spikes that must be suppressed by the
input filters
0
4.7
4.0
4.7
4.0
0
0.3
300
250
4.7
4.0
100
3.45
300
1000
50
Port Timing
tPV Output data valid
tPS Input data setup time
100
tPH Input data hold time
1
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
200
FAST MODE
I2C-bus
MIN MAX
0 400
1.3 —
0.6 —
0.6 —
0.6 —
0—
0.1 0.9
50 —
100 —
1.3 —
0.6
20 + 0.1 Cb1
20 + 0.1 Cb1
300
300
50
— 200
100 —
1—
UNITS
kHz
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
SDA
tF
SCL
S
tLOW
tR
tSU;DAT
tF
tHD;STA
tHD;STA
tHD;DAT tHIGH
tSU;STA
SR
Figure 10. Definition of timing
tSP tR tBUF
tSU;STD
P
S
SU01469
2004 Aug 20
11

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