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PDF PCA9501 Data sheet ( Hoja de datos )
| Número de pieza | PCA9501 | |
| Descripción | 8-bit I2C and SMBus I/O port with interrupt/ 2-kbit EEPROM and 6 address pins | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
PCA9501
8-bit I2C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
Product data
Supersedes data of 2002 Sep 27
2003 Sep 12
Philips
Semiconductors
1 page  
Philips Semiconductors
8-bit I2C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
Product data
PCA9501
FUNCTIONAL DESCRIPTION
WRITE PULSE
DATA FROM
SHIFT REGISTER
POWER-ON
RESET
DQ
FF
CI
S
100 µA
VDD
I/O0 TO I/O7
VSS
READ PULSE
DATA TO
SHIFT REGISTER
DQ
FF
CI
S
Figure 4. Simplified schematic diagram of each I/O
TO INTERRUPT LOGIC
SW00788
DEVICE ADDRESSING
Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.
SLAVE ADDRESS
SLAVE ADDRESS
0 A5 A4 A3 A2 A1 A0 R/W
1 A5 A4 A3 A2 A1 A0 R/W
(a) I/O EXPANDER
(b) MEMORY
FIXED
HARDWARE
PROGRAMMABLE
a.
FIXED
HARDWARE
PROGRAMMABLE
b.
Figure 5. PCA9501 slave addresses
SW02006
The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write
operation.
CONTROL REGISTER
The PCA9501 contains a single 8-bit register called the Control Register, which can be written and read via the I2C bus. This register is sent
after a successful acknowledgment of the slave address.
It contains the I/O operation information.
2003 Sep 12
5
5 Page 
Philips Semiconductors
8-bit I2C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
Product data
PCA9501
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 16).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 17).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 18).
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 16. Bit transfer
SW00542
SDA
SDA
SCL
S
SCL
P
START CONDITION
STOP CONDITION
Figure 17. Definition of start and stop conditions
SW00543
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
Figure 18. System configuration
MASTER
TRANSMITTER/
RECEIVER
SW00544
2003 Sep 12
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PCA9501.PDF ] | |
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