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PDF PCA8581P Data sheet ( Hoja de datos )

Número de pieza PCA8581P
Descripción 128 x 8-bit EEPROM with I2C-bus interface
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCA8581P Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
PCA8581; PCA8581C
128 × 8-bit EEPROM with I2C-bus
interface
Product specification
Supersedes data of 1996 Aug 19
File under Integrated Circuits, IC12
1997 Apr 02

1 page




PCA8581P pdf
Philips Semiconductors
128 × 8-bit EEPROM with I2C-bus interface
Product specification
PCA8581; PCA8581C
7 CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.3 Bit transfer.
7.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SCL
S
START condition
SDA
SCL
P
STOP condition
MBA608
Fig.4 Definition of START and STOP conditions.
1997 Apr 02
5

5 Page





PCA8581P arduino
Philips Semiconductors
128 × 8-bit EEPROM with I2C-bus interface
Product specification
PCA8581; PCA8581C
11 AC CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and
VIH with an input voltage swing of VSS to VDD.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
I2C-bus timing (see Fig.11; note 1)
fSCL
tSP
tBUF
tSU;STA
tHD;STA
tLOW
tHIGH
tr
tf
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
SCL LOW to data out valid
STOP condition set-up time
−−
−−
4.7
4.7
4.0
4.7
4.0
−−
−−
250
0
−−
4.0
100 kHz
100 ns
− µs
− µs
− µs
− µs
− µs
1.0 µs
0.3 µs
ns
ns
3.4 µs
− µs
Note
1. A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to
use it”. This brochure may be ordered using the code 9398 393 40011.
handbook, full pagewidth
PROTOCOL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
t SU;STA
t LOW t HIGH
1 / f SCL
SCL
t BUF
tr
tf
SDA
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
t HD;STA
t SU;DAT
t HD;DAT
t VD;DAT
MBD820
t SU;STO
1997 Apr 02
Fig.11 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
11

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