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PDF PCA8565TS Data sheet ( Hoja de datos )

Número de pieza PCA8565TS
Descripción Real time clock/calender
Fabricantes NXP Semiconductors 
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No Preview Available ! PCA8565TS Hoja de datos, Descripción, Manual

PCA8565
Real time clock/calender
Rev. 01 — 31 March 2003
Product data
1. General description
The PCA8565 is a CMOS real time clock/calendar optimized for low power
consumption. A programmable clock output, interrupt output and voltage-low detector
are also provided. All address and data are transferred serially via a two-line
bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address
register is incremented automatically after each written or read data byte.
2. Features
s Provides year, month, day, weekday, hours, minutes and seconds based on
32.768 kHz quartz crystal
s Century flag
s Clock operating voltage: 1.8 to 5.5 V
s Extended operating temperature range: 40 to +125 °C
s Low backup current; typical 0.5 µA at VDD = 3.0 V and Tamb = 25 °C
s 400 kHz two-wire I2C-bus interface (at VDD = 1.8 to 5.5 V)
s Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz,
32 Hz and 1 Hz)
s Alarm and timer functions
s Integrated oscillator capacitor
s Internal power-on reset
s I2C-bus slave address: read A3H and write A2H
s Open-drain interrupt pin.
3. Applications
s Automotive
s Industrial
s Other applications that require a wide operating temperature range.
4. Quick reference data
Table 1:
Symbol
VDD
Quick reference data
Parameter
supply voltage
IDD
Tamb
supply current
ambient temperature
Conditions
I2C-bus active; fSCL = 400 kHz;
Tamb = 40 to +125 °C
fSCL = 400 kHz
Min Typ Max Unit
1.8 -
5.5 V
--
40 -
820
+125
µA
°C

1 page




PCA8565TS pdf
Philips Semiconductors
PCA8565
Real time clock/calender
handbook, halfpage
VDD
MGR887
period of battery
operation
normal power
operation
Vlow
Fig 4. Voltage-low detection.
VL set
t
8.6 Register organization
Table 4: Binary formatted registers overview
Bit positions labelled as x are not implemented, those labelled with 0 should always be written with logic 0.
Address Register name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
00H
control/status 1
TEST1 0
STOP 0
TESTC 0
0
01H
control/status 2
0
0
0
TI/TP AF TF AIE
0DH
CLKOUT control
FE
x
x
x
x
x
FD1
0EH timer control TE x x x x x TD1
0FH timer
<timer countdown value>
Bit 0
0
TIE
FD0
TD0
Table 5: BCD formatted registers overview
Bit positions labelled as x are not implemented.
Address Register name
BCD format tens nibble
BCD format units nibble
Bit 7
23
Bit 6
22
Bit 5
21
Bit 4
20
Bit 3
23
Bit 2
22
Bit 1
21
Bit 0
20
02H seconds
VL
<seconds 00 to 59 coded in BCD>
03H minutes
x
<minutes 00 to 59 coded in BCD>
04H hours
xx
<hours 00 to 23 coded in BCD>
05H days
xx
<days 01 to 31 coded in BCD>
06H weekdays
xxxxx
<weekdays 0 to 6>
07H
months/century
C
x
x
<months 01 to 12 coded in BCD>
08H years
<years 00 to 99 coded in BCD>
09H minute alarm AE
<minute alarm 00 to 59 coded in BCD>
0AH hour alarm
AE x
<hour alarm 00 to 23 coded in BCD>
0BH day alarm
AE x
<day alarm 01 to 31 coded in BCD>
0CH
weekday alarm
AE
x
x
x
x
<weekday alarm 0 to 6>
9397 750 10695
Product data
Rev. 01 — 31 March 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 26

5 Page





PCA8565TS arduino
Philips Semiconductors
PCA8565
Real time clock/calender
3. Clear STOP (control/status 1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
8.8 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the
long start-up times experienced by these types of circuits, a mechanism has been
built in to disable the POR and hence speed up on-board test of the device. The
setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a
specific order as shown in Figure 5. All timings are required minimums.
Once the override mode has been entered, the device immediately stops being reset
and normal operation may commence i.e. entry into the EXT_CLK test mode via
I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC.
TESTC must be set to logic 1 before re-entry into the override mode is possible.
Setting TESTC to logic 0 during normal operation has no effect except to prevent
entry into the POR override mode.
handbook, full pagewidth
SDA
500 ns
2000 ns
SCL
8 ms
power up
Fig 5. POR override sequence.
override active
MGM664
9. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal (see Figure 6).
9397 750 10695
Product data
Rev. 01 — 31 March 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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