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PDF PCA5010H Data sheet ( Hoja de datos )
| Número de pieza | PCA5010H | |
| Descripción | Pager baseband controller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCA5010
Pager baseband controller
Product specification
File under Integrated Circuits, IC17
1998 Nov 02
1 page  
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I(D1), Q(D0)
2
AFCOUT
AT
DAC
WATCHDOG
TONE
GENERATOR
6 MHz
OSCILLATOR
VIND
VDD(DC)
VSS(DC)
VBAT
VDD
VSS
2
2
RESETIN
RESOUT
DC/DC
CONVERTER
POWER
CONTROLLER
MODE AND
TEST CONTROL
3
ALE, PSEN, EA TCLK
DIGITAL
FILTER
ZERO-IF
4L DEMODULATOR
SYMBOL SAMPLING
CLOCK RECOVERY
RAM
OTP/ROM
PROCESSOR
80C51
INTERRUPT
CONTROL
TIMER 0
TIMER 1
various clocks
PORT
CONTROL
P0
P2
P3
P1
UART SIO
I2C SIO
VPP
8
P0
8 P2
4
P3
(T0, T1,
INT0, INT1)
7 P1
(SDA, SCL,
RXD, TXD)
WAKE-UP
RTC
CLOCK
CLOCK
GENERATOR CORRECTION
supplied by VBAT
76.8 kHz
OSCILLATOR
XTL2
XTL1
MGR107
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
6.4 Memory organization
The PCA5010 has a program memory (OTP) plus data
memory (RAM) on-chip. The device has separate address
spaces for Program and Data Memory (see Fig.4). If Ports
P0 and P2 are not used as I/O signals these pins can be
used to address up to 64 kbytes of external program
memory. In this case, the CPU generates the latch signal
(ALE) for an external address latch and the read strobe
(PSEN) for external Program Memory. External data
memory is not supported.
6.4.1 PROGRAM MEMORY
After reset the CPU begins execution of the program
memory at location 0000H. The program memory can be
implemented in either internal OTP or external memory.
If the EA pin is strapped to VDD, then program memory
fetches are directed to the internal program memory. If the
EA pin is strapped to VSS, then program memory fetches
are directed to external memory.
Programming the on-chip OTP is detailed in Chapter 15.
Usually Philips will deliver programmed parts to a
customer. Supply of blank engineering samples is
possible, but then Philips cannot give any guarantee on
the programmability and retention of the program memory.
6.4.2 DATA MEMORY
The PCA5010 contains 1280 bytes internal RAM
(consisting of 256 bytes standard RAM and 1024 bytes
AUX-RAM) and Special Function Registers (SFRs).
Figure 4 shows the internal data memory space divided
into the lower 128 bytes the upper 128 bytes and the SFR
space and 1024 bytes auxiliary RAM. Internal RAM
locations 0 to 127 are directly and indirectly addressable.
Internal RAM locations 128 to 255 are only indirectly
addressable. The SFR locations 128 to 255 bytes are only
directly addressable and the auxiliary RAM is indirectly
addressable as external RAM (MOVX). External Data
Memory (EDM) is not supported.
6.4.3 SPECIAL FUNCTION REGISTERS
The second 128 bytes are the address locations of the
special function registers. Table 1 shows the special
function registers space. The SFRs include the port
latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct
addressing. There are 128 bit addressable locations in the
SFR address space (those SFRs whose addresses are
divisible by eight).
handbook, full pagewFidFthFFH
EXTERNAL
7FFFH
INTERNAL
(EAN = 1)
EXTERNAL
(EAN = 0)
0
PROGRAM MEMORY
3FFH
FFH
80H
7FH
00H
INDIRECT
DIRECT
ADDRESSING ADDRESSING
INDIRECT AND
DIRECT
ADDRESSING
INDIRECT
ADDRESSING
WITH DPTR
INDIRECT
ADDRESSING
WITH Ri, DPTR
100H
0FFH
000H
Internal RAM SFR space
Internal XRAM
DATA MEMORY
External XRAM
is not supported
MGL459
Fig.4 Memory map.
1998 Nov 02
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCA5010H.PDF ] | |
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