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PDF PCA1487 Data sheet ( Hoja de datos )
| Número de pieza | PCA1487 | |
| Descripción | 32 kHz watch circuits with adaptive motor pulse | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
PCA148x series
32 kHz watch circuits with adaptive
motor pulse
Product specification
Supersedes data of 1998 Mar 26
File under Integrated Circuits, IC16
1998 Apr 21
1 page  
Philips Semiconductors
32 kHz watch circuits with adaptive motor
pulse
Product specification
PCA148x series
Voltage level detector
The supply voltage is compared with the internal voltage
reference VEOL every minute. The first voltage level
detection is carried out 30 ms after RESET.
When the detected VDD voltage level is greater than VEOL,
the circuit operates in normal mode (Fig.3).
If the battery end-of-life is detected (VDD < VEOL), the
detection and stage control is switched OFF and the
waveform of stage 6 will be executed. To indicate this
condition the waveform is produced in bursts of 4 pulses
every 4 s.
Detection of motor movement
After a motor pulse, the motor is short-circuited to VDD for
1 ms. Afterwards the energy in the motor inductor will be
dissipated to measure only the current generated by the
induced motor voltage. During the time tDI (dissipation of
energy time) all switches shown in Fig.4 are open to
reduce the current as fast as possible. The current will now
flow through the diodes D3 and D2, or D4 and D1. Then
the first of 52 possible measurement cycles (tMC) starts to
measure the induced current.
P1 D1
D2 P2
VDD
L1
M1 MOTOR
M2
L2
N1 D3
D4 N2
V SS
MSA941
Fig.4 Motor driving and detecting circuit.
1998 Apr 21
5
5 Page 
Philips Semiconductors
32 kHz watch circuits with adaptive motor
pulse
Product specification
PCA148x series
Power-on reset
For correct operation of the Power-on reset the rise time of
VDD from 0 V to 2.1 V should be less than 0.1 ms.
All resettable flip-flops are reset. Additionally the polarity of
the first motor pulse is positive: VM1 − VM2 ≥ 0 V.
Customer testing
An output frequency of 32 Hz is provided at RESET (pin 8)
to be used for exact frequency measurement. Every
minute a jitter occurs as a result of the inhibition, which
occurs 90 to 150 ms after disconnecting the RESET from
VDD.
Connecting the RESET to VDD stops the motor pulses
leaving them in a 3-state mode and sets the motor pulse
width for the next available motor pulse to stage 1. A 32 Hz
signal without jitter is produced at the TEST pin. Debounce
time RESET = 14.7 to 123.2 ms.
Connecting RESET to VSS activates Tests 1 and 2 and
disables the inhibition.
Test 1, VDD > VEOL. Normal function takes place except
that the motor pulse period is tT1 = 125 ms instead of tT,
and the motor pulse stage is reduced every second
instead of every 8 minutes. At TEST a speeded-up
8 minute signal is available.
Test 2, VDD < VEOL. Motor pulses of stage 6 are produced,
with a time period of tT2 = 31.25 ms.
Test and reset modes are terminated by disconnecting the
RESET pin.
Test 3, VDD > 5.1 V. Motor pulses without chopping are
produced, with a time period of tT3 = 31.25 ms and
n × 122 µs to check the contents of the EEPROM.
At TEST a speeded-up cycle for motor pulse period signal
tT is available at 1024 times its normal frequency.
Decreasing VDD voltage level to lower than 2.5 V between
two motor pulses returns the circuit to normal operating
conditions.
AVAILABLE TYPES
Refer to Chapters “Ordering information” and “Functional description and testing”.
SHORT
TYPE
NUMBER
1 485
DELIVERY
FORMAT(1)
U/7
PERIOD
tT
(s)
1
PULSE
WIDTH
tP
(ms)
5.8
1 486
U/7
1 5.8
1 487
U/5
1 7.8
DRIVE
(%)
75
75
75
SPECIFICATIONS
DETECTION
CRITERION
BATTERY
EEPROM
EOL
DETECTION
REMARKS
P = 1 yes yes
N=2
P=1
N=2
yes
no
P = 2 yes yes
N=3
Note
1. U = Chip in trays; U/5 = wafer; U/7 = chip with bumps on tape.
1998 Apr 21
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet PCA1487.PDF ] | |
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