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Número de pieza IH5352CBP
Descripción Quad SPST/ CMOS RF/Video Switch
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
IH5352
July 1999 File Number 3134.2
Quad SPST, CMOS RF/Video Switch
The IH5352 is a quad SPST, CMOS monolithic switch which
uses a “Series/Shunt” (“T” switch) configuration to obtain
high OFF isolation while maintaining good frequency
response in the ON condition.
Construction of remote and portable video equipment with
extended battery life is facilitated by the extremely low
current requirements. Switching speeds are typically
tON = 150ns and tOFF = 80ns. “Break-Before-Make”
switching is guaranteed.
Switch ON resistance is typically 40- 50with ±15V power
supplies, increasing to typically 175for ±5V supplies.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
IH5352CPE
IH5352CBP
0 to 70
0 to 70
16 Ld PDIP
20 Ld SOIC
PKG.
NO.
E16.3
M20.3
Pinouts
IH5352
(PDIP)
TOP VIEW
IIN1 1
S1 2
IIN2 3
S2 4
IIN3 5
S3 6
IIN4 7
S4 8
16 D1
15 V+
14 D2
13 GND
12 D3
11 V-
10 D4
9 VL
Features
• rDS(ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
• Switch Attenuation Varies Less Than 3dB From DC to
100MHz
• OFF Isolation at 10MHz . . . . . . . . . . . . . . . . . . . . . >70dB
• Crosstalk Isolation at 10MHz . . . . . . . . . . . . . . . . . >60dB
• Compatible With TTL, CMOS Logic
• Wide Operating Power Supply Range
• Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . <1µA
• “Break-Before-Make” Switching
• Fast Switching (Typ) . . . . . . . . . . . . . . . . . . . . 80ns/150ns
Applications
• Video Switch
• Communications Equipment
• Disk Drives
• Instrumentation
• CATV
Functional Diagram
SWITCH STATE SHOWN FOR LOGIC “0” INPUT
S1 D1
IIN1
S2 D2
IIN2
IH5352
(SOIC)
TOP VIEW
IIN1 1
S1 2
NC 3
IIN2 4
S2 5
IIN3 6
S3 7
NC 8
IIN4 9
S4 10
20 D1
19 V+
18 NC
17 D2
16 GND
15 D3
14 V-
13 NC
12 D4
11 VL
S3 D3
IIN3
S4 D4
IIN4
TRUTH TABLE
LOGIC
SWITCHES
0 Off
1 On
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




IH5352CBP pdf
IH5352
Detailed Description
Figure 5 shows the internal circuit of one channel of the
IH5352. Here, a shunt switch is closed, and the two series
switches are open when the video switch channel is open or
off. This provides much better isolation between the input
and output terminals than a simple series switch does,
especially at high frequencies. The result is excellent off-
isolation in the Video and RF frequency ranges when
compared to conventional analog switches.
The control input level shifting circuitry is very similar to that
of the IH5140 series of Analog Switches, and gives very high
speed, guaranteed “Break-Before-Make” action, low static
power consumption and TTL compatibility.
SWITCH
SOURCE
(VIDEO INPUT)
LOGIC
CONTROL
INPUT
DRIVER
TRANSLATOR
SHUNT
SWITCH
SWITCH
DRAIN
(VIDEO
OUTPUT)
NOTE: 1 channel of 4 shown.
FIGURE 5. INTERNAL SWITCH CONFIGURATION
Typical Applications
Charge Compensation Techniques
Charge injection results from the signals out of the level
translation circuit being coupled through the gate-channel
and gate-source/drain capacitances to the switch inputs and
outputs. This feedthrough is particularly troublesome in
Sample-and-Hold or Track-and-Hold applications, as it
causes a Sample (Track) to Hold offset. The IH5352 has a
typical injected charge of 30pC-50pC (corresponding to
30mV-50mV on a 1000pF capacitor), at VS-D of about 0V.
This Sample (Track) to Hold offset can be compensated by
bringing in a signal equal in magnitude but of the opposite
polarity. The circuit of Figure 6 accomplishes this charge
injection compensation by using one side of the device as a
S & H (T & H) switch, and the other side as a generator of a
compensating signal. The 1kpotentiometer allows the user
to adjust the net injected charge to exactly zero for any
analog voltage in the -5V to +5V range.
Since individual parts are very consistent in their charge
injection, it is possible to replace the potentiometer with a
pair of fixed resistors, and achieve less than 5mV error for
all devices without adjustment.
An alternative arrangement, using a standard TTL inverter to
generate the required inversion, is shown in Figure 7. The
capacitor needs to be increased, and becomes the only method
of adjustment. A fixed value of 22pF is good for analog values
referred to ground, while 35pF is optimum for AC coupled
signals referred to -5V as shown in the figure. The choice of -5V
is based on the virtual disappearance at this analog level of the
transient component of switching charge injection. This
combination will lead to a virtually “glitch-free” switch.
75
15V
1µF
VOUT
S1 V+
ANALOG
INPUT
D1
IN1
V-
5V
VL S2
D2
-15V
1kCERMET
NOT WIRE
WOUND (NOTE)
IN2
GND
75
10pF
CHOLD
1000pF
+3V
0V
TTL IN (STROBE)
1µF
NOTE: Adjust pot for 0mVP-P step at VOUT with no analog (AC)
signal present.
FIGURE 6. CHARGE INJECTION COMPENSATION
5

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