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Número de pieza PCA1070
Descripción Multistandard programmable analog CMOS transmission IC
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
DATA SHEET
PCA1070
Multistandard programmable
analog CMOS transmission IC
Product specification
Supersedes data of 1996 Mar 06
File under Integrated Circuits, IC03
1997 Jun 20

1 page




PCA1070 pdf
Philips Semiconductors
Multistandard programmable analog
CMOS transmission IC
Product specification
PCA1070
FUNCTIONAL DESCRIPTION
All values in the Chapter “Functional description” are
typical unless stated otherwise.
Line interface
DC VOLTAGE DROP
Power for the PCA1070 and its peripheral circuits is
obtained from the telephone line. The IC develops its own
supply voltage at VDD and regulates its DC voltage drop
between pins SLPE and VSS. This voltage (VSLPE) can be
programmed via the I2C-bus interface between
3.1 to 5.9 V and is default at 4.7 V (see Table 8).
The DC line voltage at pin LN can be calculated using the
following equation:
VLN = VSLPE + (Iline ILN) × RLN-SLPE
where:
ILN = DC bias current flowing into pin LN
(3 mA if Iline > 17 mA)
RLN-SLPE = external 20 resistor between
LN and SLPE.
At line currents below 6 mA the DC voltage VSLPE is
automatically adjusted to a lower value. This means that
the operation of more sets, connected in parallel, is
possible with reduced sending and receiving levels and
relaxed performance. At line currents below 16 mA the DC
bias current ILN is reduced from 3 mA to a lower value to
ensure maximum possible transmit level capability under
all line current conditions.
SET IMPEDANCE
In normal conditions Iline >> ILN and the static behaviour is
equivalent to a voltage regulator diode with a series
resistor RLN-SLPE. In the audio frequency range the
dynamic impedance ZLN is determined mainly by the
internal component Zset = Ra + (Rb // C). The equivalent
impedance ZLN is shown in Fig.3. The values of Ra, Rb
and C can be programmed via the I2C-bus interface
(see Tables 9, 10 and 11).
handbook, halfpage
RLN-SLPE
SLPE
Leq
VSLPE
CP CREG CLSI
REG LSI
RP RLSI
Ca
Zset
Ra
LN
Rb C
MGE342 VSS
Fig.3 Equivalent impedance ZLN.
where:
Ca = DC blocking capacitor (influence negligible at
f 300 Hz for given value of CLSI)
CLSI = capacitor at pin LSI (100 nF)
CP = internal capacitor (12 nF)
CREG = capacitor at pin REG (470 nF)
Leq = artificial inductor
(= RP × RLN-SLPE × CREG = 10.1 H at VSLPE = 4.7 V)
RLN-SLPE = DC slope resistance (20 )
RP = internal resistor (1075 kat VSLPE = 4.7 V)
RLSI = internal resistor (240 k).
SUPPLY FOR PERIPHERAL CIRCUITS
The supply voltage VDD can be used for peripheral
circuitry. The supply capabilities depend on the
programmed DC voltage drop VSLPE and on several other
parameters as given in the following equation:
VDD = VSLPE (IDD + Ip + IVP) × RSLPEVDD
where:
IDD = internal current consumption PCA1070 (2.3 mA)
Ip = current to peripheral circuitry
IVP = current taken from VP for electret microphone
RSLPEVDD = external resistor between SLPE and VDD.
1997 Jun 20
5

5 Page





PCA1070 arduino
Philips Semiconductors
Multistandard programmable analog
CMOS transmission IC
Product specification
PCA1070
Table 4 The control word format for the slave receiver
DEVICE ADDRESS
SUB ADDRESS
DATA/CONTROL BYTE
S 0 1 0 0 0 1 0 0(1) A I7 I6 I5 I4 I3 I2 I1 I0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
Note
1. This bit is R/W.
Table 5 Bit arrangement of each data byte used in the control word: PCA1070 receive (see note 1)
FUNCTION
DC voltage
Sidetone and set
impedance
Sending channel
Receiving
channel
Control
SUB
ADDRESS
H00
H01
H02
H03
H04
H05
H06
D7
ZOSB3
ZOSP3
DLT
RFC
PD1
D6
VDC2
ZOSB2
ZOSP2
ZSB2
HPL
PD0
D5
VDC1
ZOSB1
ZOSP1
ZSB1
GMA5
GRA5
D4
VDC0
ZOSB0
ZOSP0
ZSB0
GMA4
GRA4
RRG
D3
ZOSA3
ZSP3
GMA3
GRA3
RM
D2
ZOSA2
ZSA2
ZSP2
GMA2
GRA2
SM
D1
ZOSA1
ZSA1
ZSP1
GMA1
GRA1
D0
DST
ZOSA0
ZSA0
ZSP0
GMA0
GRA0
DPI
Note
1. The bits that are not indicated must be set to logic 0.
Table 6 The control word format for the slave transmitter
DEVICE ADDRESS
DATA/STATUS BYTE
S 0 1 0 0 0 1 0 1(1) A D7 D6 D5 D4 D3 D2 D1 D0
Note
1. Change in direction of R/W bit.
A
P
Table 7 PCA1070 send
FUNCTION
PCA1070 status
D7
PRES(1)
D6
D5 D4 D3 D2 D1 D0
LC4(2) LC3(2) LC2(2) LC1(2) LC0(2)
Notes
1. Indicates if PCA1070 has received internal reset; PRES will be set to logic 1 with internal reset and is set to logic 0
after reading the register via the I2C-bus.
2. Information about value of line current.
1997 Jun 20
11

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