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PDF PC97317VUL Data sheet ( Hoja de datos )

Número de pieza PC97317VUL
Descripción PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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- February 1998
PRELIMINARY
February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel® peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the Plug
and Play ISA Specification Version 1.0a, May 5, 1994, and
meets specifications defined in the PC97 Hardware Design
Guide. It features a Controller/Extender that is fully compli-
ant with Advanced Configuration and Power Interface (AC-
PI) Revision 1.0 requirements.
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) sup-
port, a full IEEE 1284 Parallel Port, 24 General-Purpose In-
put/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOGtimer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four ba-
sic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Among the most advanced members of National Semicon-
ductor’s highly successful SuperI/O family, the PC87317VUL
offers:
q Full compatibility with ACPI Revision 1.0 requirements
q Compliancy with PC97 Hardware Design Guide speci-
fications, including PC97 LED support
q Advanced RTC, including timekeeping and APC func-
tionality
q 24 GPIO bit ports
q FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
DMA
IRQ Channels
Data and
Control Ports
Control
Data Control
Floppy Drive
Interface
Plug and Play
(PnP)
Keyboard + Mouse
Controller (KBC)
(Logical Devices 0 & 1)
Real-Time Clock
(RTC and APC)
(Logical Device 2)
X-Bus
Floppy Disk
Controller (FDC)
(Logical Device 3)
µP Address
Data and
Control
IEEE 1284
Serial Port
Serial Port
General-Purpose I/O
Power
Parallel Port
with IR (UART2)
(UART1)
(GPIO) Registers Management (PM)
(Logical Device 4) (Logical Devices 5) (Logical Devices 6) (Logical Device 7) (Logical Device 8)
Data Handshake Serial Infrared
Interface Interface
Serial
Interface
I/O Ports
Control
TRI-STATE® and WATCHDOGare trademarks of National Semiconductor Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
© 1998 National Semiconductor Corporation
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PC97317VUL pdf
Table of Contents
Table of Contents
Highlights....................................................................................................................................................... 1
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM ......................................................................................................... 16
1.2 SIGNAL/PIN DESCRIPTIONS ................................................................................................... 17
2.0 Configuration
2.1 HARDWARE CONFIGURATION ............................................................................................... 27
2.1.1 Wake Up Options ........................................................................................................ 27
2.1.2 The Index and Data Register Pair ............................................................................... 27
2.1.3 The Strap Pins ............................................................................................................. 28
2.2 SOFTWARE CONFIGURATION ............................................................................................... 28
2.2.1 Accessing the Configuration Registers ........................................................................ 28
2.2.2 Address Decoding ....................................................................................................... 28
2.3 THE CONFIGURATION REGISTERS ....................................................................................... 29
2.3.1 Standard Plug and Play (PnP) Register Definitions .................................................... 30
2.3.2 Configuration Register Summary ................................................................................ 33
2.4 CARD CONTROL REGISTERS ................................................................................................ 37
2.4.1 PC87317 SID Register ................................................................................................ 37
2.4.2 PC97317 SID Register ................................................................................................ 37
2.4.3 SuperI/O Configuration 1 Register (SIOC1) ................................................................ 37
2.4.4 SuperI/O Configuration 2 Register (SIOC2) ................................................................ 38
2.4.5 Programmable Chip Select Configuration Index Register ........................................... 38
2.4.6 Programmable Chip Select Configuration Data Register ............................................ 39
2.4.7 SuperI/O Configuration 3 Register (SIOC3) ................................................................ 39
2.4.8 PC97317 SRID Register .............................................................................................. 39
2.4.9 SuperI/O Configuration F Register (SIOCF), Index 2Fh .............................................. 40
2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) .................................................... 40
2.5.1 SuperI/O KBC Configuration Register ......................................................................... 40
2.6 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) .................................................. 40
2.6.1 SuperI/O FDC Configuration Register ......................................................................... 40
2.6.2 Drive ID Register ......................................................................................................... 41
2.7 PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ............................... 41
2.7.1 SuperI/O Parallel Port Configuration Register ............................................................. 41
2.8 UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) .................... 42
2.8.1 SuperI/O UART2 Configuration Register ..................................................................... 42
2.9 UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................ 42
2.9.1 SuperI/O UART1 Configuration Register ..................................................................... 42
2.10 PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ...................................... 42
2.10.1 CS0 Base Address MSB Register ............................................................................... 43
2.10.2 CS0 Base Address LSB Register ................................................................................ 43
2.10.3 CS0 Configuration Register ......................................................................................... 43
2.10.4 Reserved ..................................................................................................................... 43
2.10.5 CS1 Base Address MSB Register ............................................................................... 43
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PC97317VUL arduino
Table of Contents
7.5 SHARP-IR MODE – DETAILED DESCRIPTION ..................................................................... 163
7.6 SIR MODE – DETAILED DESCRIPTION ................................................................................ 163
7.7 CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................ 164
7.7.1 Consumer-IR Transmission ....................................................................................... 164
7.7.2 Consumer-IR Reception ............................................................................................ 164
7.8 FIFO TIME-OUTS .................................................................................................................... 165
7.8.1 UART, SIR or Sharp-IR Mode Time-Out Conditions ................................................. 165
7.8.2 Consumer-IR Mode Time-Out Conditions ................................................................. 165
7.8.3 Transmission Deferral ............................................................................................... 165
7.9 AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 165
7.11 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 166
7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) ................................. 166
7.11.2 Interrupt Enable Register (IER) ................................................................................. 167
7.11.3 Event Identification Register (EIR) ............................................................................ 168
7.11.4 FIFO Control Register (FCR) ..................................................................................... 170
7.11.5 Link Control Register (LCR) and Bank Selection Register (BSR) ............................. 171
7.11.6 Bank Selection Register (BSR) ................................................................................. 172
7.11.7 Modem/Mode Control Register (MCR) ...................................................................... 172
7.11.8 Link Status Register (LSR) ........................................................................................ 174
7.11.9 Modem Status Register (MSR) .................................................................................. 175
7.11.10 Scratchpad Register (SPR) ....................................................................................... 175
7.11.11 Auxiliary Status and Control Register (ASCR) .......................................................... 176
7.12 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS ......................................... 176
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), .............................. 177
7.12.2 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 177
7.13 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 177
7.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ........................... 178
7.13.2 Extended Control Register 1 (EXCR1) ...................................................................... 179
7.13.3 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 180
7.13.4 Extended Control and Status Register 2 (EXCR2) .................................................... 180
7.13.5 Reserved Register ..................................................................................................... 180
7.13.6 TX_FIFO Current Level Register (TXFLV) ................................................................ 180
7.13.7 RX_FIFO Current Level Register (RXFLV) ............................................................... 181
7.14 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 181
7.14.1 Module Revision ID Register (MRID) ........................................................................ 181
7.14.2 Shadow of Link Control Register (SH_LCR) ............................................................. 181
7.14.3 Shadow of FIFO Control Register (SH_FCR) ............................................................ 182
7.14.4 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 182
7.15 BANK 4 – IR MODE SETUP REGISTER ................................................................................ 182
7.15.1 Reserved Registers ................................................................................................... 182
7.15.2 Infrared Control Register 1 (IRCR1) .......................................................................... 182
7.15.3 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 182
7.15.4 Reserved Registers ................................................................................................... 182
7.16 BANK 5 – INFRARED CONTROL REGISTERS ..................................................................... 183
7.16.1 Reserved Registers ................................................................................................... 183
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