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PDF IDT821054 Data sheet ( Hoja de datos )
| Número de pieza | IDT821054 | |
| Descripción | QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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QUAD PROGRAMMABLE PCM
CODEC WITH MPI INTERFACE
IDT821054
FEATURES
• 4-channel CODEC with on-chip digital filters
• Software selectable A/µ-law, linear code conversion
• Meets ITU-T G.711 - G.714 requirements
• Programmable digital filters adapting to systemdemands:
- AC impedance matching
- Transhybrid balance
- Frequency response correction
- Gain setting
• Supports two programmable PCM buses
• Flexible PCM interface with up to 128 programmable time slots,
data rate from 512 kbits/s to 8.192 Mbits/s
• MPI control interface
• Broadcast mode for coefficient setting
• 7 SLIC signaling pins (including 2 debounced pins) per channel
• Fast hardware ring trip mechanism
FUNCTIONAL BLOCK DIAGRAM
• 2 programmable tone generators per channel for testing,
ringing and DTMF generation
• 1 programmable FSK generator for sending Caller-ID messages
• Two programmable chopper clocks
• Master clock frequency selectable: 1.536 MHz, 1.544 MHz, 2.048
MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or
8.192 MHz
• Advanced test capabilities:
- 3 analog loopback tests
- 5 digital loopback tests
- Level metering function
• High analog driving capability (300 Ω AC)
• TTL/CMOS compatible digital I/O
• CODEC identification
• +5 V single power supply
• Low power consumption
• Operating temperature range: -40°C to +85°C
• Package available: 64 Pin PQFP
VIN1
VOUT1
2 Inputs
3 I/Os
2 Outputs
MCLK
CHCLK1
CHCLK2
CH1
Filter and A/D
D/A and Filter
SLIC Signaling
DSP
Core
CH3
Filter and A/D
D/A and Filter
SLIC Signaling
CH2 CH4
PLL and Clock
Generation
General Control
Logic
MPI Interface
PCM Interface
VIN3
VOUT3
2 Inputs
3 I/Os
2 Outputs
DR1
DR2
DX1
DX2
RESET INT12 INT34 CCLK CS CI CO FS BCLK TSX1 TSX2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
1
FEBRUARY 26, 2003
DSC-6035/5
1 page  
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
Figure - 1
Figure - 2
Figure - 3
Figure - 4
Figure - 5
Figure - 6
Figure - 7
Figure - 8
Figure - 9
Figure - 10
Figure - 11
Figure - 12
Figure - 13
LIST OF FIGURES
An Example of the MPI Interface Write Operation .............................................................................................................................. 9
An Example of the MPI Interface Read Operation (ID = 81H)............................................................................................................. 9
Sampling Edge Selection Waveform................................................................................................................................................. 10
Signal Flow for Each Channel ........................................................................................................................................................... 11
Debounce Filter ................................................................................................................................................................................. 13
General Procedure of Sending Caller-ID Signal................................................................................................................................ 14
A Recommended Procedure of Programming the FSK Generator ................................................................................................... 15
Clock Timing...................................................................................................................................................................................... 40
MPI Input Timing ............................................................................................................................................................................... 41
MPI Output Timing ............................................................................................................................................................................ 41
Transmit and Receive Timing............................................................................................................................................................ 42
Typical Frame Sync Timing (2 MHz Operation) ................................................................................................................................ 42
Coe-RAM Mapping............................................................................................................................................................................ 43
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
2.2 DSP PROGRAMMING
2.2.1 SIGNAL PROCESSING
Several blocks are programmable for signal processing. This allows
users to optimize the performance of the IDT821054 for the system.
Figure - 4 shows the signal flow for each channel and indicates the
programmable blocks.
The programmable digital filters are used to adjust gain and
impedance, balance transhybrid and correct frequency response. All the
coefficients of the digital filters can be calculated automatically by a
software provided by IDT. When users provide accurate SLIC model,
impedance and gain requirements, this software will calculate all the
coefficients automatically. After loading these coefficients to the
coefficient RAM of the IDT821054, the final AC characteristics of the line
card (consists of SLIC and CODEC) will meet the ITU-T specifications.
Analog
@2 MHz
VIN LPF/AA ∑ −∆
Transmit Path
@64 KHz
@16 KHz
LREG1: CS[3]
CS[3] = 1: enable (normal)
CS[3] = 0: disable (bypass)
@8 KHz
Level Meter
TS
PCM Highway
D1
GTX D2
LPF FRX
HPF
CMP
TSA DX1/DX2
GIS IMF ECF
VOUT
LPF/SC
∑ −∆
LREG1: CS[2]
CS[2] = 1: enable (normal)
CS[2] = 0: disable (cut)
U1 UF
GRX U2 LPF
LREG1: CS[0]
CS[0] = 1: enable (normal)
CS[0] = 0: disable (cut)
LREG1: CS[1]
CS[1] = 1: enable (normal)
CS[1] = 0: disable (cut)
Receive Path
FRR EXP TSA
FSK
Dual
Tone
CUT-OFF-PCM
DR1/DR2
Bold Black Framed: Programmable Filters
Fine Black Framed: Fixed Filters
Abbreviation List:
LPF/AA: Anti-Alias Low-pass Filter
LPF/SC: Smoothing Low-pass Filter
LPF: Low-pass Filter
HPF: High-pass Filter
GIS: Gain for Impedance Scaling
D1: 1st Down Sample Stage
D2: 2nd Down Sample Stage
U1: 1st Up Sample Stage
U2: 2nd Up Sample Stage
UF: Up Sampling Filter (64 k - 128 k)
Figure - 4 Signal Flow for Each Channel
IMF: Impedance Matching Filter
ECF: Echo Cancellation Filter
GTX: Gain for Transmit Path
GRX: Gain for Receive Path
FRX: Frequency Response Correction for Transmit
FRR: Frequency Response Correction for Receive
CMP: Compression
EXP: Expansion
TSA: Time Slot Assignment
2.2.2 GAIN ADJUSTMENT
The analog gain and digital gain of each channel can be adjusted
separately in the IDT821054.
For each individual channel, the analog A/D gain in the transmit path
can be selected as 0 dB or 6 dB. The selection is done by the GAD bit in
LREG9. It is 0 dB by default.
For each individual channel, the analog D/A gain in the receive path
can be selected as 0 dB or -6 dB. The selection is done by the GDA bit
in LREG9. It is 0 dB by default.
For each individual channel, the digital gain in the transmit path
(GTX) is programmable from -3 dB to +12 dB with minimum 0.1 dB step.
If the CS[5] bit in local register LREG1 is ‘0’, the GTX filter is disabled. If
the CS[5] bit is ‘1’, the GTX is programmed by the coefficient RAM.
For each individual channel, the digital gain in the receive path
(GRX) is programmable from -12 dB to +3 dB with minimum 0.1 dB step.
If the CS[7] bit in LREG1 is ‘0’, the GRX filter is disabled. If the CS[7] bit
is ‘1’, the GRX is programmed by the coefficient RAM.
2.2.3 IMPEDANCE MATCHING
The IDT821054 provides a programmable feedback path from VIN to
VOUT for each channel. This feedback synthesizes the two-wire
impedance of the SLIC. The programmable Impedance Matching Filter
(IMF) and Gain of Impedance Scaling filter (GIS) work together to realize
impedance matching. If the CS[0] bit in LREG1 is ‘0’, the IMF is
disabled. If the CS[0] bit is ‘1’, the IMF coefficient is programmed by the
coefficient RAM. If the CS[2] bit in LREG1 is ‘0’, the GIS filter is disabled.
If the CS[2] bit is ‘1’, the GIS coefficient is programmed by the coefficient
RAM.
11
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