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PDF IDT821034 Data sheet ( Hoja de datos )

Número de pieza IDT821034
Descripción QUAD PCM CODEC WITH PROGRAMMABLE GAIN
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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OCTAL E1 SHORT HAUL
LINE INTERFACE UNIT
IDT82V2058
FEATURES
Fully integrated octal E1 short haul line interface which
supports 120E1 twisted pair and 75E1 coaxial appli-
cations
Selectable single rail or dual rail mode and AMI or HDB3
line encoder/decoder
Built-in transmit pre-equalization meets G.703
Selectable transmit/receive jitter attenuator meets ETSI
CTR12/13, ITU G.736, G.742 and G.823 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/analog LOS detector meets ITU G.775 and ETS 300
233
ITU G.772 non-intrusive monitoring for in-service testing
for any one of channel1 to channel7
Low impedance transmit drivers with tri-state
Selectable hardware and parallel/serial host interface
Local and remote loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection
without relays
JTAG boundary scan for board test
3.3V supply with 5V tolerant I/O
Low power consumption
Operating temperature range: -40°C to +85°C
Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA)
and 160-pin Plastic Ball Grid Array (PBGA) packages
FUNCTIONAL BLOCK DIAGRAM
RTIPn
RRINGn
Slicer
Analog
Peak
Loopback Detector
LOS
Detector
CLK&Data
Recovery
(DPLL)
Digital
Loopback
One of Eight Identical Channels
Jitter
Attenuator
HDB3/AMI
Decoder
Remote
Loopback
AIS
Detector
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
Jitter
Attenuator
HDB3/AMI
Encoder
TCLKn
TDn/TDPn
BPVIn/TDNn
G.772
Monitor
Clock
Generator
Transmit
All Ones
Control Interface
Register
File
JTAG TAP
VDD IO
VDDT
VDDD
VDDA
Figure - 1. Block Diagram
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
© 2002 Integrated Device Technology, Inc.
1
JANUARY 2003
DSC-6038/9

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IDT821034 pdf
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
Type
I
Pin No.
QFP144 BGA160
Description
37 N2 TDn: Transmit Data for Channel 0~7
30 L2 When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data
80 L13 on TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3 line
73 N13 code rules before being transmitted to the line.
108 B13
101 D13 BPVIn: Bipolar Violation Insertion for Channel 0~7
8 D2 Bipolar violation insertion is available in Signal Rail mode 2 (see table-1) with AMI enabled. A low-
1 B2 to-high transition on this pin will make the next logic one to be transmitted on TDn pin the same
polarity as the previous pulse, and violate the AMI rule. This is for testing.
38 N3
31 L3 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
79 L12 When the device is in Dual Rail mode, the NRZ data to be transmitted for positive/negative pulse
72 N12 is input on this pin. Data on TDPn/TDNn are active high and sampled into the device on falling
109 B12 edges of TCLKn. The line code in Dual Rail mode is as the follows :
102 D12
TDPn TDNn Output Pulse
7 D3
144 B3
0 0 Space
0 1 Negative Pulse
1 0 Positive Pulse
1 1 Space
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the
corresponding channel into Single Rail mode 1 (see table-1 on Page13).
I 36 N1 TCLKn: Transmit Clock for Channel 0~7
29 L1 The clock of 2.048 MHz to be transmitted is input on this pin. The transmit data at TDn/TDPn or
81 L14 TDNn is sampled into the device on falling edges of TCLKn.
74 N14 Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in
107 B14 Transmit All One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts
100 D14 MCLK as the time reference.
9 D1 If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver
2 B1 output ports become high impedance.
The different operating modes of TCLKn are summarized as follows:
MCLK
TCLKn
Transmitter Mode
Clocked
Clocked
Normal operation
Clocked High (16 MCLK) Transmit All One (TAO) signals to line side in the
corresponding transmit channel.
Clocked Low (64 MCLK) Corresponding transmit channel is set into power down state.
High/Low TCLK1 is clocked TCLKn is clocked Normal operation
TCLKn is high Transmit All One (TAO) signals to the line
(16 TCLK1) side in the corresponding transmit channel.
TCLKn is low Corresponding transmit channel is set into
(64 TCLK1) power down state.
The receive path is not affected by the status of TCLK1.
When MCLK is high, all receive paths just slice the incoming
data stream. When MCLK is low, all the receive paths are
powered down.
High/Low TCLK1 is not All eight transmitters (TTIPn & TRINGn) will be in high
available impedance state.
(High/Low)
5

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IDT821034 arduino
IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
OVERVIEW
The IDT82V2058 is a fully integrated octal short-haul line interface
unit, which contains eight transmit and receive channels for use in E1
applications. The receiver performs clock and data recovery. As an
option, the raw sliced data (no retiming) can be output to the system.
Transmit equalization is implemented with low-impedance output driv-
ers that provide shaped waveforms to the transformer, guaranteeing
template conformance. A selectable jitter attenuation may be placed in
the receive path or the transmit path. Moreover, multiple testing func-
tions, such as error detection, loopback and JTAG boundary scan are
also provided. The device is optimized for flexible software control
through a serial or parallel host mode interface. Hardware control is
also available. Figure-1 shows One of the Eight Identical Channels
operation.
SYSTEM INTERFACE
The system interface of each channel can be configured to
operate in different modes:
1. Single Rail interface with clock recovery.
2. Dual Rail interface with clock recovery.
3. Dual Rail interface with data recovery (that is, with raw data slic-
ing only and without clock recovery).
Therefore, each signal pin on system side has multiple functions
depending on which operation mode the device is in.
Dual Rail interface consists of TDPn1, TDNn, TCLKn, RDPn, RDNn
and RCLKn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface; data received from the RTIPn
and RRINGn at the line interface are transferred to RDPn and RDNn
while the recovered clock extracting from the received data stream
outputs on RCLKn. In Dual Rail operation, the clock/data recovery
mode is selectable. Dual Rail interface with clock recovery shown in
Figure-3 is a default configuration mode. Dual Rail interface with data
recovery is shown in Figure-4. Pin RDPn and RDNn, in this condition,
are raw RZ slice output and internally connected to an EXOR which is
fed to the RCLKn output for external clock recovery applications.
In Single Rail mode, data transmitted from TDn appears on TTIPn
and TRINGn at the line interface. Data received from the RTIPn and
RRINGn at the line interface appears on RDn while the recovered
clock extracting from the received data stream outputs on RCLKn.
When the device is in Single Rail interface, the selectable AMI or
HDB3 line encoder/decoder is available and any code violation in the
received data will be indicated at the CVn pin. The Single Rail mode
can be divided into 2 sub-modes. Single Rail mode1, whose interface
is composed of TDn, TCLKn, RDn, CVn and RCLKn, is realized by
pulling pin TDNn to high for more than 16 consecutive TCLK cycles.
Single Rail mode 2, whose interface is composed of TDn, TCLKn,
RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in e-
CRS2 and bit SING in e-SING. The difference between them is that, in
the latter mode bipolar violation can be inserted via pin BPVIn if AMI
line code is selected.
The configuration of different system interface is summarized in
Table-1.
CLOCK EDGES
The active edge of RCLK and SCLK(serial interface clock) are also
selectable. If pin CLKE is Low, the active edge of RCLK is the rising
edge, as for SCLK, that is falling edge. On the contrary, if CLKE is
High, the active edge of RCLK is the falling edge and that of SCLK is
rising edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active
high, and those output signals are valid on the active edge of RCLK
and SCLK respectively. See Table-2 for details. However, in dual rail
mode without clock recovery, pin CLKE is used to set the active level
for RDPn/RDNn raw slicing output: High for active high polarity and
Low for active low. It should be noted that data on pin SDI are always
active high and is sampled on the rising edge of SCLK. The data on
pin TD/TDP or BPVI/TDN are also always active high but is sampled
on the falling edge of TCLK, despite the level on CLKE.
RTIPn
RRINGn
Slicer
LOS
Detector
CLK&Data
Recovery
(DPLL)
One of Eight Identical Channels
Jitter
Attenuator
HDB3/
AMI
Decoder
TTIPn
TRINGn
Peak
Detector
Line
Driver
Waveform
Shaper
Jitter
Attenuator
HDB3/
AMI
Encoder
Transmit
All Ones
Figure - 3. Dual Rail Interface with Clock Recovery 3
NOTE:
1. The footprint ‘n’ (n = 0 - 7) indicates one of the eight channels
2. The first letter “e-”indicates expanded register.
3. The grey blocks are bypassed and the dotted blocks are selectable
11
LOSn
RCLKn
RDPn
RDNn
TCLKn
TDPn
TDNn

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