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PDF IDT7MPV6255 Data sheet ( Hoja de datos )
| Número de pieza | IDT7MPV6255 | |
| Descripción | 256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPCO | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Integrated Device Technology, Inc.
256KB AND 512KB SECONDARY
CACHE MODULES FOR THE
PowerPC™
IDT7MPV6253
IDT7MPV6255/56
FEATURES
• For CHRP based PowerPC™ systems.
• Asynchronous and pipelined burst SRAM options in the
same module pinout
• Low-cost, low-profile card edge module with 178 leads
• Uses Burndy Computerbus™ connector, part number
ELF182KSC-3Z50
• Operates with external PowerPC CPU speeds up to
66MHz
• Separate 5V (±5%) and 3.3V (+10/-5%) power supplies
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Presence Detect output pins allow the system to deter-
mine the particular cache configuration.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of
secondary caches intended for use with PowerPC CPU-
based systems. The IDT7MPV6253 uses IDT’s 71V256 32K
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use
IDT’s 71V432 32K x 32 pipelined synchronous burst static
RAMs in plastic surface mount packages mounted on a
multilayer epoxy laminate (FR-4) board. In addition, each of
the modules uses the IDT 71216 16K x 15 Cache-Tag static
RAM and IDT FCT logic. Extremely high speeds are achieved
using IDT’s high-reliability, low cost CMOS technology.
The low profile card edge package allows 178 signal leads
to be placed on a package 5.06" long, a maximum of 0.250"
thick and a maximum of 1.08" tall. The module space savings
versus discrete components allows the OEM to design addi-
tional functions onto the system or to shrink the size of the
motherboard for reduced cost.
All inputs and outputs are LVTTL-compatible, and operate
from separate 5V (±5%) and 3.3V (+10/-5%) power supplies.
Multiple GND pins and on-board decoupling capacitors en-
sure maximum protection from noise.
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION
A14 - A26 13
13
ALE
ADDRA0
ADDRA1
SRAM OE1
WE#0
WE#1
WE#2
WE#3
STANDBY
A14 - A26 13
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
8K x 12
Tag Field
8K x 2
Status
ADDRA0
ADDRA1
SRAM OE0
8 DH0 - DH7 WE#4
8 DH8 - DH15 WE#5
8 DH16 - DH23 WE#6
8 DH24 - DH31 WE#7
STANDBY
12 A2 - A13
TMATCH
DIRTYOUT
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
1
PD0
PD1
PD2
PD3
8 DL0 - DL7
8 DL8 - DL15
8 DL16 - DL23
8 DL24 - DL31
drw 01
JUNE 1996
DSC-3608/2
1 page  
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC5 = 5.0V ± 5%, VCC3 = 3.3V ± 10%, TA = 0°C to 70°C)
Symbol
|ILI|
|ILI|
|ILO|
VOL
VOH
ICC3
ICC5
ISB3
ISB31
Parameter
Input Leakage Current
(Address)
Input Leakage Current
(Data and Control)
Output Leakage Current
Output Low Voltage
Output HighVoltage
Operating 3.3V Power
Supply Current
Operating 5V Power
Supply Current
Standby 3.3V Power
Supply Current
Full Standby 3.3V Power
Supply Current
ISB5 Standby 5V Power
Supply Current
Test Condition
VCC5 = Max, VIN = GND to VCC
VCC3 = Max
VCC5 = Max, VIN = GND to VCC
VCC3 = Max
VOUT = 0V to VCC3, VCC3 = Max.
IOL = 8mA, VCC3 = Min.
IOH= –4mA, VCC3 = Min.
VCC3 = Max., STANDBY ≤ VIL,
f = fMAX, Outputs Open
VCC5 = Max., STANDBY ≤ VIL,
f = fMAX, Outputs Open
VCC3 = Max., STANDBY ≥ VIH,
f = fMAX, Outputs Open
VCC3 = Max., STANDBY ≥ VCC3 - 0.2V, f = 0,
VIN ≤ 0.2V or VIN ≥ VCC3 - 0.2V,
Outputs Open
VCC5 = Max., STANDBY ≥ VIH
f = fMAX, Outputs Open
Min.
—
—
—
—
2.4
—
—
—
—
—
’53
Max.
20
10
10
0.4
—
1000
290
100
30
30
’55
Max.
30
10
10
0.4
—
500
290
100
30
30
’56
Max.
50
Unit
µA
20 µA
20 µA
0.4 V
—V
590 mA
290 mA
190 mA
50 mA
30 mA
tbl 09
AC TEST CONDITIONS – 3.3V POWER SUPPLY
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
tbl 10
+3.3V
320Ω
DATA OUT
350Ω
30pF*
*including scope and jig capacitances
Figure 1. Output Load
drw 05
+3.3V
320Ω
DATA OUT
350Ω
5pF*
*including scope and jig capacitances
Figure 2. Output Load
(for tOHZ, tCHZ, tOLZ and tCLZ)
drw 06
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT7MPV6255.PDF ] | |
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