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PDF IDT7MMV4101S12BGI Data sheet ( Hoja de datos )

Número de pieza IDT7MMV4101S12BGI
Descripción 128K x 24 Three Megabit 3.3V CMOS Static RAM
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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No Preview Available ! IDT7MMV4101S12BGI Hoja de datos, Descripción, Manual

128K x 24 Three Megabit
3.3V CMOS Static RAM
IDT7MMV4101
Features
x High density 3 megabit 3.3V static RAM
x Low profile 119 lead, 14mm x 22mm
BGA (Ball Grid Array)
x Fast RAM access times: 10,12,15ns
x Single 3.3V power supply
x Multiple Vcc & GND pins for maximum noise immunity
x Inputs/outputs directly LVTTL compatible
x Commercial (0O C to +70O C) Industrial (-40O C to +85O C)
temperature options
– Commercial: 10 / 12 / 15 ns
– Industrial: 12 / 15 ns
Description
The IDT7MMV4101 is a three megabit static RAM constructed on an
multilayer laminate substrate using three 3.3V, 128K x 8 (IDT71V124)
static RAMS encapsulated in a Ball Grid Array (BGA).
The IDT7MMV4101 is packaged in a plastic BGA. The BGA configu-
ration allows 119 leads to be placed on a package 14mm by 22mm. At a
maximum of 3.5mm high, this low-profile surface mount package is ideal
for ultra dense systems.
All inputs and outputs of the IDT7MMV4101 are LVTTL compatible and
operate from a single 3.3V supply. Full asynchronous circuitry requires
no clocks or refresh for operation and provides equal access and cycle
times for ease of use.
Pin Names
I/O0 - 23
A0 - 16
CS
WE
OE
VCC
GND
NC
Data Inputs/Outputs
Addresses
Chip Select
Write Enable
Output Enable
Power
Ground
No Connect
Pin Configuration
Functional Block Diagram
17
A0-16
CS
WE
OE
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
8
I/O0-7
8
I/O8-15
8
I/O16-23
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,
4083 tbl 01
7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC
6 A4 A8 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A12 A16
5 A3 A7 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A11 A15
4 A2 CS NC GND GND GND GND GND GND GND GND GND GND GND NC WE OE
3 A1 A6 NC GND VCC GND VCC GND VCC GND VCC GND VCC GND NC A10 A14
2 A0 A5 NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC A9 A13
1 NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC
,
A B C D E F G HJ K L M N P RTU
Top View
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©2003 Integrated Device Technology, Inc.
1
JANUARY 2003
DSC-4083/05

1 page




IDT7MMV4101S12BGI pdf
IDT7MMV4101
128K x 24 Three Megabit 3.3V CMOS Static RAM
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
tRC
tAA
OE
CS
DATAOUT
tOE
tOLZ (5)
tCLZ(5)
tACS(3)
HIGH IMPEDANCE
Commercial and Industrial Temperature Ranges
tOHZ (5)
tCHZ(5)
DATAOUT VALID
,
.
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Timing Waveform of Read Cycle No. 2(1,2,4)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
.4083 drw 05
6.452

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