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PDF IDT7MB4048S25P Data sheet ( Hoja de datos )

Número de pieza IDT7MB4048S25P
Descripción 512K x 8 CMOS STATIC RAM MODULE
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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Integrated Device Technology, Inc.
512K x 8
CMOS STATIC RAM MODULE
IDT7MB4048
FEATURES:
• High-density 4-megabit (512K x 8) Static RAM module
• Fast access time: 25ns (max.)
Surface mounted plastic packages on a 32-pin, 600 mil
FR-4 DIP substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MB4048 is a 4-megabit (512K x 8) Static RAM
module constructed on a multilayer epoxy laminate (FR-4)
substrate using four 1 megabit SRAMs and a decoder. The
IDT7MB4048 is available with access times as fast as 25ns.
The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting
in the JEDEC footprint in a package 1.6 inches long and 0.6
inches wide.
All inputs and outputs of the IDT7MB4048 are TTL-com-
patible and operate from a single 5V supply. Fully asynchro-
nous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
PIN CONFIGURATION
A 18
A 16
A 14
A 12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
DIP
TOP VIEW
Vcc
A 15
A 17
WE
A 13
A8
A9
A 11
OE
A 10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
2675 drw 01
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
CS
WE
OE
19
512K x 8
RAM
8
I/O
2675 drw 02
PIN NAMES
I/O0-7
A0-18
CS
WE
OE
VCC
GND
Data Inputs/Outputs
Addresses
Chip Select
Write Enable
Output Enable
Power
Ground
2675 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
7.11
DECEMBER 1995
DSC-2675/6
1

1 page




IDT7MB4048S25P pdf
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
ADDRESS
tWC
OE
CS
WE
DATAOUT
DATAIN
tAW
tAS
tWP (7)
tWR
tWHZ (6)
tOHZ (6)
(4)
tOW (6)
tDH
tDW
DATA VALID
tOHZ (6)
(4)
2675 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
ADDRESS
CS
WE
DATAIN
tAS
tWC
tAW
tCW
tWR
tDW tDH
DATA VALID
2675 drw 10
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
7.11 5

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