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PDF IDT7MB4045S20M Data sheet ( Hoja de datos )

Número de pieza IDT7MB4045S20M
Descripción 256K x 32 CMOS STATIC RAM MODULE
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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No Preview Available ! IDT7MB4045S20M Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
256K x 32
CMOS STATIC RAM MODULE
IDT7MP4045
IDT7MP4145
FEATURES:
• High density 1 megabyte static RAM module
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)
• Low profile 64 pin ZIP (Zig-zag In-line vertical Package)
or 64 pin SIMM (Single In-line Memory Module) for
IDT7MP4045 and 72 pin SIMM (Single In-line Memory
Module) for IDT7MP4145
• Very fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Inputs/outputs directly TTL-compatible
PIN CONFIGURATION – 7MP4045(1)
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
1
23
45
67
89
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
26 27
28 29
30 31
32 ZIP, SIMM
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
CS2
PD0 – GND
PD1 – GND
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
TOP
34
VIEW 33
36 35
38 37
40 39
42 41
44 43
45
46
48 47
49
50
52 51
53
54
55
56
57
58
59
60
61
62
64 63
CS4
A17
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
2703 drw 01
NOTE:
1. Pins 2 and 3 (PD0 and PD1) are read by the user to determine the density
of the module. If PD0 reads GND and PD1 reads GND, then the module
has a 256K depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
DESCRIPTION:
The IDT7MP4045/4145 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate using 8
256K x 4 static RAMs in plastic SOJ packages. Availability of
four chip select lines (one for each group of two RAMs)
provides byte access. The IDT7MP4045 is available with
access time as fast as 10ns with minimal power consumption.
The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig-
zag In-line vertical Package)or a 64 pin SIMM (Single In-line
Memory Module) where as the 7MP4145 is packaged in a 72
pin SIMM (Single In-line Memory Module). The 4045 ZIP
configuration allows 64 pins to be placed on a package 3.65
inches long and 0.365 inches wide. The 7MP4045 ZIP is only
0.585 inches high, this low profile package is ideal for systems
with minimum board spacing while the SIMM configuration
allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4045/4145 are TTL-
compatible and operate from a single 5V supply. Full asyn-
chronous circuitry requires no clocks or refresh for operation
and provides equal access and cycle times for ease of use.
Identification pins are provided for applications in which
different density versions of the module are used. In this way,
the target system can read the respective levels of PD pins to
determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel
covered by 30 micro-inches minimum of selective gold.
FUNCTIONAL BLOCK DIAGRAM
CS1 CS2 CS3 CS4
18
ADDRESS
WE
OE
PIN NAMES
I/O031
A017
CS1–4
WE
OE
PD0–1
VCC
GND
NC
256K x 32
RAM
2 PD
888
I/O 0-31
8
2703 drw 02
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
2703 tbl 01
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
15.2
SEPTEMBER 1996
DSC-2703/7
1

1 page




IDT7MB4045S20M pdf
IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
OE
CS
DATA OUT
tRC
tAA
tACS
tCLZ (5)
tOE
tOLZ (5)
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATA VALID
tAA
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
COMMERCIAL TEMPERATURE RANGE
tOH
tOHZ (5)
tCHZ (5)
2703 drw 07
t OH
DATA VALID
2703 drw 08
CS
DATAOUT
tCLZ (5)
tACS
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition LOW.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
tCHZ (5)
2703 drw 06
15.2 5

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