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PDF IDT7M1003 Data sheet ( Hoja de datos )

Número de pieza IDT7M1003
Descripción 128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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®
Integrated Device Technology, Inc.
128K x 8
64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE
IDT7M1001
IDT7M1003
FEATURES
• High-density 1M/512K CMOS Dual-Port Static RAM
module
• Fast access times:
—Commercial 35, 40ns
—Military 40, 50ns
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (leadless chip carriers) compo-
nents on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL-compatible
PIN CONFIGURATION(1)
VCC
R/WL
OEL
CSL
SEML
A0L
A1L
GND
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L
I/O 0L
I/O 1L
I/O 2L
I/O 3L
I/O 4L
I/O 5L
I/O 6L
I/O 7L
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64 GND
63 R/WR
62 OER
61 CSR
60 SEMR
59 A0R
58 A1R
57 A2R
56 A3R
55 A4R
54 A5R
53 A6R
52 A7R
51 A8R
50 A9R
49 A10R
48 A11R
47 A12R
46 A13R
45 A14R
44 A15R
43 A16R
42 GND
41 I/O0R
40 I/O1R
39 I/O2R
38 I/O3R
37 I/O4R
36 I/O5R
35 I/O6R
34 I/O7R
33 VCC
2804 drw 01
DIP
TOP VIEW
NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected
to GND for proper operation of the module.
DESCRIPTION:
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 high-
speed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two IDT FCT138 decoders or depopu-
lated using only four IDT7006s and two decoders.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (SEM) “hand-
shake” signaling. The IDT7M1001/1003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users re-
sponsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1001/1003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with di-
mensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 35ns over the commercial temperature range are
available.
All inputs and outputs of the IDT7M1001/1003 are TTL-
compatible and operate from a single 5V supply. Fully asyn-
chronous circuitry is used, requiring no clocks or refreshing for
operation of the module.
All IDT military module semiconductor components are
manufacured in compliance with the latest revision of MIL-
STD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN NAMES
Left Port
Right Port
A (0–16)L
I/O (0–7)L
R/WL
A (0–16)R
I/O (0–7)R
R/WR
CSL
CSR
OEL
OER
SEML
SEMR
VCC
GND
Description
Address Inputs
Data Inputs/Outputs
Read/Write Enables
Chip Select
Output Enable
Semaphore Control
Power
Ground
2804 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
7.5
MARCH 1995
DSC-7066/5
1

1 page




IDT7M1003 pdf
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = -55°C to +125°C and 0°C to +70°C)
–35
Symbol Parameter
Min. Max.
Read Cycle
tRC Read Cycle Time
35 —
tAA
tACS(2)
Address Access Time
Chip Select Access Time
— 35
— 35
tOE Output Enable Access Time
— 20
tOH
tCLZ(1)
tCHZ(1)
tOLZ(1)
tOHZ(1)
tPU(1)
tPD(1)
Output Hold From Address Change
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Chip Select to Power-Up Time
Chip Disable to Power-Down Time
3—
3—
— 20
3—
— 20
0—
— 50
tSOP
SEM Flag Update Pulse (OE or SEM)
15 —
Write Cycle
tWC
tCW(2)
Write Cycle Time
Chip Select to End-of-Write
35 —
30 —
tAW
tAS1(3)
Address Valid to End-of-Write
Address Set-up to Write Pulse Time
30 —
5—
tAS2 Address Set-up to CS Time
0—
tWP
tWR(4)
Write Pulse Width
Write Recovery Time
30 —
0—
tDW
tDH(4)
tOHZ(1)
tWHZ(1)
tOW(1, 4)
Data Valid to End-of-Write
Data Hold Time
Output Disable to Output in High-Z
Write Enable to Output in High-Z
Output Active from End-of-Write
25 —
0—
— 20
— 20
0—
tSWRD
SEM Flag Write to Read Time
15 —
tSPS SEM Flag Contention Window
15 —
Port-to-Port Delay Timing
tWDD(5) Write Pulse to Data Delay
tDDD(5) Write Data Valid to Read Data Valid
— 60
— 45
NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM CS VIL and SEM VIH. To access semaphore, CS VIH and SEM VIL.
3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition.
4. For CS controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
–40
Min. Max.
40 —
— 40
— 40
— 25
3—
3—
— 20
3—
— 20
0—
— 50
15 —
40 —
35 —
35 —
5—
0—
35 —
0—
30 —
0—
— 20
— 20
0—
15 —
15 —
— 65
— 50
–50
Min. Max.
50 —
— 50
— 50
— 30
3—
3—
— 25
3—
— 25
0—
— 50
15 —
50 —
40 —
40 —
5—
0—
40 —
0—
35 —
0—
— 25
— 25
0—
15 —
15 —
— 70
— 55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2804 tbl 09
7.5 5

5 Page





IDT7M1003 arduino
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
ORDERING INFORMATION
IDT XXXX
Device
type
A
Power
999
Speed
A
Package
A
Process/
Temperature
range
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BLANK Commercial (0°C to +70°C)
B Military (-55°C to +125°C)
Semiconductor components compliant to
MIL-STD-883, Class B
C Sidebraze DIP (Dual In-line Package)
35 (Commercial Only)
40
50 (Military Only)
Nanoseconds
S Standard Power
7M1001 128K x 8 Dual-Port Static RAM Module
7M1003 64K x 8 Dual-Port Static RAM Module
2804 drw 15
7.5 11

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