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PDF IDT79RV4650133MS Data sheet ( Hoja de datos )
| Número de pieza | IDT79RV4650133MS | |
| Descripción | EMBEDDED 64-BIT ORION RISC MICROPROCESSOR | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Integrated Device Technology, Inc.
EMBEDDED
64-BIT ORION™ RISC
MICROPROCESSOR
IDT79R4650™
IDT79RV4650™
FEATURES
• High-performance embedded 64-bit microprocessor
- 64-bit integer operations
- 64-bit registers
- 80MHz, 100MHz, 133MHz operation frequency
• High-performance DSP capability
- 66.7 Million Integer Multiply-Accumulate Operations/
sec @ 133 MHz
- 44 MFlops floating point operations @133MHz
• High-performance microprocessor
- 133 MIPS at 133MHz
- 66.7 M Mul-Add/second at 133MHz
- 44 MFLOP/s at 133MHz
- >300,000 dhrystone (2.1)/sec capability at 133MHz
(175 dhrystone MIPS)
• High level of integration
- 64-bit, 133 MIPS integer CPU
- 44MFlops Single precision floating-point unit
- 8KB instruction cache; 8KB data cache
- Integer multiply unit with 66.7M Mul-Add/sec
• Low-power operation
- Active power management powers-down inactive units
- Standby mode
• Upward software compatible with IDT RISController Family
• Large, efficient on-chip caches
- Separate 8kB Instruction and 8kB Data caches
- Over 1500MB/sec bandwidth from internal caches
- 2-set associative
- Write-back and write-through support
- Cache locking to facilitate deterministic response
• Bus compatible with ORION family
- System interfaces to 67 MHz, provides bandwidth up to
533 MB/S
- Direct interface to 32-bit wide or 64-bit wide systems
- Synchronized to external reference clock for multi-master
operation
• Improved real-time support
- Fast interrupt decode
- Optional cache locking
BLOCK DIAGRAM:
133 MIPS 64-bit ORION CPU
64-bit register file
64-bit adder
Load aligner
Store Aligner
Logic Unit
High-Performance
Integer Multiply
System Control Coprocessor 44MFLOPS Single-Precision FPA
Address Translation/
Cache Attribute Control
FP register file
Exception Management
Functions
Pack/Unpack
FP Add/Sub/Cvt/
Div/Sqrt
FP Multiply
Control Bus
Instruction Bus
Data Bus
Instruction Cache
Set A
(Lockable)
Instruction Cache
Set B
32-/64-bit
Synchronized
System Interface
Data Cache
Set A
(Lockable)
Data Cache
Set B
The IDT logo is a registered trademark and ORION, R4650, RV4650, R4600, R3081, R3052, R3051, R3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 1996 Integrated Device Technology, Inc.
5.8
MARCH 1996
DSC3149/2
1
1 page  
IDT79R4650
COMMERCIAL TEMPERATURE RANGE
Table 2 gives the latencies of some of the floating-point
instructions in internal processor cycles.
Operation
Instruction
Latency
ADD
4
SUB
4
MUL
8
DIV 32
SQRT
31
CMP
3
FIX 4
FLOAT
6
ABS
1
MOV
1
NEG
1
LWC1
2
SWC1
1
Table 2: Floating-Point Operation
Floating-Point General Register File
The floating-point register file is made up of thirty-two 32-
bit registers. These registers are used as source or target
registers for the single-precision operations.
References to these registers as 64-bit registers (as
supported in the R4600) will cause a trap to be signalled to
the integer unit.
The floating-point control register space contains two
registers; one for determining configuration and revision
information for the coprocessor and one for control and
status information. These are primarily involved with
diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
lation is controlled, exceptions are handled, and operating
modes are controlled (kernel vs. user mode, interrupts
enabled or disabled, cache features). In addition, the
R4650 includes registers to implement a real-time cycle
counting facility, which aids in cache diagnostic testing,
assists in data error detection, and facilitates software
debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic
interrupt.
Table 3 shows the CP0 registers of the R4650.
Number Name
0 IBase
1 IBound
2 DBase
3 DBound
4-7, 10, 20- —
25, 29, 31
8 BadVAddr
9 Count
11 Compare
12 Status
13 Cause
14 EPC
15 PRId
16 Config
17 CAlg
18 IWatch
19 DWatch
Function
Instruction address space base
(new in R4650)
Instruction address space bound
(new in R4650)
Data address space base (new in
R4650)
Data address space bound (new in
R4650)
Not used
Virtual address on address excep-
tions
Counts every other cycle
Generate interrupt when Count
= Compare
Miscellaneous control/status
Exception/Interrupt information
Exception PC
Processor ID
Cache and system attributes
Cache attributes for the eight
512MB regions of the virtual
address space — new register
Instruction breakpoint virtual
address
Data breakpoint virtual address
System Control Co-processor (CP0)
The system control co-processor in the MIPS archi-
tecture is responsible for the virtual to physical address
translation and cache protocols, the exception control
system, and the diagnostics capability of the processor. In
the MIPS architecture, the system control co-processor
(and thus the kernel software) is implementation
dependent.
In the R4650, significant changes in CP0 relative to the
R4600 have been implemented. These changes are
designed to simplify memory management, facilitate
debug, and speed real-time processing.
System Control Co-Processor Registers
The R4650 incorporates all system control co-processor
(CP0) registers on-chip. These registers provide the path
through which the virtual memory system’s address trans-
26 ECC
Used in cache diagnostics
27 CacheErr Cache diagnostics
28 TagLo
Cache index
30 ErrorEPC CacheError exception PC
Table 3: R4650 CPO Registers
Operation modes
The R4650 supports two modes of operation: user mode
and kernel mode.
Kernel mode operation is typically used for exception
handling and operating system kernel functions, including
CP0 management and access to IO devices. In kernel
mode, software has access to the entire address space
and all of the co-processor 0 registers, and can select
whether to enable co-processor 1 accesses. The processor
5.8 5
5 Page 
IDT79R4650
COMMERCIAL TEMPERATURE RANGE
Thermal Considerations
The R4650 utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
The R4650 is packaged using cavity down packaging in a
208-pin MQUAD.
The R4650 utilizes the MQUAD package (the “MS”
package), which is an all-aluminum package with the die
attached to a normal copper lead frame mounted to the
aluminum casing. Due to the heat-spreading effect of the
aluminum, the MQUAD package allows for an efficient
thermal transfer between the die and the case. The
aluminum offers less internal resistance from one end of
the package to the other, reducing the temperature
gradient across the package and therefore presenting a
greater area for convection and conduction to the PCB for
a given temperature. Even nominal amounts of airflow will
dramatically reduce the junction temperature of the die,
resulting in cooler operation.
The R4650 is guaranteed in a case temperature range of
0° to +85° C. The type of package, speed (power) of the
device, and airflow conditions affect the equivalent ambient
temperature conditions that will meet this specification.
The equivalent allowable ambient temperature, TA, can
be calculated using the thermal resistance from case to
ambient (∅CA) of the given package. The following
equation relates ambient and case temperatures:
DATA SHEET REVISION HISTORY
Changes to version dated September 1995:
AC Electrical Characteristics:
- In System Interface Parameters tables (R4650 and
RV4650), Data Setup and Data Hold minimums
changed.
TA = TC - P * ∅CA
where P is the maximum power consumption at hot
temperature, calculated by using the maximum ICC specifi-
cation for the device.
Typical values for ∅CA at various airflows are shown in
Table 6.
Preliminary
∅CA
Airflow (ft/min) 0 200 400 600 800 1000
208 MQUAD
21 13 10 9 8 7
Table 6: Thermal Resistance (∅CA) at Various Airflows
Note that the R4650 implements advanced power
management to substantially reduce the average power
dissipation of the device. This operation is described in the
IDT79R4640 and IDT79R4650 RISC Processor Hardware
User’s Manual.
5.8 11
11 Page | ||
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