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PDF IDT79RV4640100DU Data sheet ( Hoja de datos )

Número de pieza IDT79RV4640100DU
Descripción LOW-COST EMBEDDED ORION RISC MICROPROCESSOR
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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Integrated Device Technology, Inc.
LOW-COST EMBEDDED
ORIONRISC
MICROPROCESSOR
IDT79R4640
IDT79RV4640
FEATURES
• High-performance embedded 64-bit microprocessor
- 64-bit integer operations
- 64-bit registers
- Based on the MIPS RISC Architecture
- 80MHz, 100MHz, 133 MHz and 150MHz operation
frequency
- 32-bit bus interface brings 64-bit power to 32-bit sys-
tem cost
• High-performance DSP capability
- 75 Million Integer Mul-Accumulate operations/sec
@150MHz
- 50 MFlops floating-point operations @150MHz
• High-performance microprocessor
- 75 M Mul-Add/second @150MHz
- 50 MFlops @150MHz
- >340,000 dhrystone (2.1)/sec capability @133MHz
(197 dhrystone MIPS)
• High level of integration
- 64-bit, 150 MHz integer CPU
- 50MFlops single-precision floating-point unit
- 8KB instruction cache; 8KB data cache
- Integer multiply unit with 75M Mul-Add/sec
• Upwardly software compatible with IDT RISController
Family
• Easily upgradable to 64-bit system
• Low-power operation
- Active power management powers-down inactive
units
- Standby mode
• Large, efficient on-chip caches
- Separate 8KB Instruction and 8KB Data caches
- Over 1800MB/sec bandwidth from internal caches
- 2-set associative
- Write-back and write-through support
- Cache locking to facilitate deterministic response
- High performance write protocols for graphics and
data communications
• Bus compatible with ORION family
- System interfaces to 67 MHz, provides bandwidth
up to 266 MB/sec
- Direct interface to 32-bit wide systems
- Synchronized to external reference clock for multi-
master operation
• Improved real-time support
- Fast interrupt decode
- Optional cache locking
BLOCK DIAGRAM
150 MHz 64-bit ORION CPU
64-bit Register File
64-bit Adder
Load Aligner
Store Aligner
Logic Unit
High-Performance
Integer Multiply
System Control Coprocessor 50MFlops Single-Precision FPA
Address Translation/
Cache Attribute Control
Exception Management
Functions
FP Register File
Pack/Unpack
FP Add/Sub/Cvt/
Div/Sqrt
FP Multiply
Control Bus
Instruction Bus
Data Bus
Instruction Cache
Set A
(Lockable)
Instruction Cache
Set B
32-bit
Synchronized
System Interface
Data Cache
Set A
(Lockable)
Data Cache
Set B
The IDT logo is a registered trademark and ORION, R4650, R4640, RV4640, R4600, R3081, R3052, R3051, R3041, R5000, R36100 , RISController, and RISCore
are trademarks of Integrated Device Technology, Inc.
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
© 1997 Integrated Device Technology, Inc.
MAY 1997
3486/1
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IDT79RV4640100DU pdf
R4640/RV4640
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
CP0 management and access to IO devices. In kernel
mode, software has access to the entire address space
and all of the co-processor 0 registers, and can select
whether to enable co-processor 1 accesses. The
processor enters kernel mode at reset, and whenever an
exception is recognized.
User mode is typically used for applications programs.
User mode accesses are limited to a subset of the virtual
address space, and can be inhibited from accessing CP0
functions.
the virtual address to form the physical address for that
reference. If the address is not within bounds, an
exception is signalled.
This facility enables multiple user processes in a single
physical memory without the use of a TLB. This type of
operation is further supported by a number of devel-
opment tools for the R4640, including real-time operating
systems and “position independent code”.
Kernel mode addresses do not use the base-bounds
registers, but rather undergo a fixed virtual to physical
address translation.
0xFFFFFFFF
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB
Debug Support
To facilitate software debug, the R4640 adds a pair of
“watch” registers to CP0. When enabled, these registers
will cause the CPU to take an exception when a
“watched” address is appropriately accessed.
0xC0000000
0xBFFFFFFF
0xA0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
0x80000000
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x7FFFFFF
User virtual address space
(useg)
Mapped, 2.0GB
0x00000000
Figure 3: Mode Virtual Addressing (32-bit mode)
Interrupt Vector
The R4640 also adds the capability to speed interrupt
exception decoding. Unlike the R4700, which utilizes a
single common exception vector for all exception types
(including interrupts), the R4640 allows kernel software to
enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing
by allowing software to avoid decoding interrupts from
general purpose exceptions.
Cache Memory
To keep the R4640’s high-performance pipeline full and
operating efficiently, the R4640 incorporates on-chip
instruction and data caches that can each be accessed in
a single processor cycle. Each cache has its own 64-bit
data path and can be accessed in parallel. The cache
subsystem provides the integer and floating-point units
with an aggregate bandwidth of over 1800 MB per second
at a pipeline clock frequency of 150MHz. The cache
subsystem is similar in construction to that found in the
R4600, although some changes have been implemented.
Table 6 is an overview of the caches found on the R4640.
Virtual-to-Physical Address Mapping
The 4GB virtual address space of the R4640 is shown
in figure 3. The 4 GB address space is divided into
addresses accessible in either kernel or user mode
(kuseg), and addresses only accessible in kernel mode
(kseg2:0).
The R4640 supports the use of multiple user tasks
sharing common virtual addresses, but mapped to
separate physical addresses. This facility is implemented
via the “base-bounds” registers contained in CP0.
When a user virtual address is asserted (load, store, or
instruction fetch), the R4640 compares the virtual address
with the contents of the appropriate “bounds” register
(instruction or data). If the virtual address is “in bounds”,
the value of the corresponding “base” register is added to
Instruction Cache
The R4640 incorporates a two-way set associative on-
chip instruction cache. This virtually indexed, physically
tagged cache is 8KB in size and is parity protected.
Because the cache is virtually indexed, the virtual-to-
physical address translation occurs in parallel with the
cache access, thus further increasing performance by
allowing these two operations to occur simultaneously.
The tag holds a 20-bit physical address and valid bit, and
is parity protected.
The instruction cache is 64-bits wide, and can be
refilled or accessed in a single processor cycle.
Instruction fetches require only 32 bits per cycle, for a
peak instruction bandwidth of 600MB/sec at 150MHz.
Sequential accesses take advantage of the 64-bit fetch to
reduce power dissipation, and cache miss refill, can write
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IDT79RV4640100DU arduino
R4640/RV4640
DATA SHEET REVISION HISTORY
Changes to version dated December 1995:
Features:
- Added 32-bit bus interface info
- Deleted items from low-power operation
descriptions.
Hardware Overview:
- Added detailed descriptions of features.
- Changed Boot Time Mode Stream table values for
mode bit 12.
DC Electrical Characteristics:
- The CIN and COUT values have been changed.
AC Electrical Characteristics:
- In System Interface Parameters tables (R4640 and
RV4640), Data Setup and Data Hold minimums
changed.
Valid Combinations:
- List of valid combinations has been corrected.
Changes to version dated March 1997:
Features:
- Added preliminary 150 MHz operation frequency
Thermal Considerations:
- Added thermally enhanced packaging (“DU”) and
drop-in heat spreader information.
- Upgraded 80 to 133MHz speed grade specs to
“final.”
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
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