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PDF IDT79RV3041 Data sheet ( Hoja de datos )
| Número de pieza | IDT79RV3041 | |
| Descripción | INTEGRATED RISController FOR LOW-COST SYSTEMS | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Integrated Device Technology, Inc.
IDT79R3041™
INTEGRATED RISController™ FOR
LOW-COST SYSTEMS
IDT79R3041
IDT79RV3041
FEATURES:
• Instruction set compatible with IDT79R3000A
and RISController Family MIPS RISC CPUs
• High level of integration minimizes system cost
— RISC CPU
— Multiply/divide unit
— Instruction Cache
— Data Cache
— Programmable bus interface
— Programmable port width support
• On-chip instruction and data caches
— 2KB of Instruction Cache
— 512B of Data Cache
• Flexible bus interface allows simple, low-cost designs
— Superset pin-compatible with RISController
— Adds programmable port width interface
(8-, 16-, and 32-bit memory sub-regions)
— Adds programmable bus interface timing support
(Extended address hold, Bus turn around time,
Read/write masks)
• Double-frequency clock input
• 16.67MHz, 20MHz, 25MHz and 33MHz operation
• 20MIPS at 25MHz
• Low cost 84-pin PLCC packaging
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-word read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• On-chip 24-bit timer
• Boot from 8-bit, 16-bit, or 32-bit wide PROMs
• Pin- and software-compatible family includes R3041, R3051,
R3052™, and R3081™
• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point emulation software
— Page Description Languages
ClkIn
Clock
Generator
Unit
Int(5:3), SInt(2:0)
TC
Master Pipeline Control SBrCond(3:2)
System Control
Coprocessor
Exception/Control
Registers
Bus Interface
Registers
PortSize
Register
Counter
Registers
Integer
CPU Core
General Registers
(32 x 32)
ALU
Shifter
Mult/Div Unit
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
2kB
Data
Cache
512B
32
4-deep
Write
Buffer
Data
Unpack
Unit
Data Bus
R3051 Superset
Bus Interface Unit
4-deep
Read
Buffer
DMA
Arbiter
BIU
Control
Data
Pack
Unit
Timing/ Interface
Control
Address/
Data
DMA Rd/Wr SysClk
Ctrl Ctrl
2905 drw 01
Figure 1. R3041 Block Diagram
RISController, R3041, R3051, R3052, R3081, ORION, IDT/sim, and IDT/kit are trademarks, and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
MARCH 1996
DSC-2905/5
1
1 page  
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
R3041.
SYSTEM USAGE
The IDT RISController family is specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems use inexpensive EPROMs, DRAMs, and
application specific peripherals.
Figure 4 shows some of the flexibility inherent in the R3041.
In this example system, which is typical of a laser printer, a 32-
bit PROM interface is used due to the size of the PDL
interpreter. An embedded system can optionally use an 8-bit
boot PROM instead. A 16-bit font/program cartridge interface
is provided for add-in cards. A 16-bit DRAM interface is used
for a low-cost page frame buffer. In this system example, a
field or manufacturing upgrade to a 32-bit page frame buffer
is supported by the boot software and DRAM controller.
Embedded systems may optionally substitute SRAMs for the
DRAMs. Finally various 8/16/32-bit I/O ports such as RS-232/
422, SCSI, and LAN as well as the laser printer engine
interface are supported. Such a system features a very low
entry price, with a range of field upgrade options including the
ability to upgrade to a more powerful member of the
RISController family.
ClkIn
IDT R3041
RISController
Address/
Data
R3051
Local Bus
Control
EPROM and
I/O Controller
DRAM
Controller
32-bit
EPROM
16-bit
Font
Cartridge
I/O
16-bit
DRAM
16-bit
Add-on
DRAM
Figure 4. Typical R3041-Based Application
2905 drw 04
5
5 Page 
IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
PIN NAME
I/O
DESCRIPTION
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31:4):
BE(3:0):
The high-order address for the transfer is presented on A/D(31:4).
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on A/D(3:0). BE(3) indicates that
A/D(31:24) will be used, and BE(0) corresponds to A/D(7:0). These
strobes are only valid for accesses to 32-bit wide memory ports. Note
that BE(3:0) can be held in-active during reads by setting the appropriate
bit of CP0; thus when latched, these signals can be directly used as Write
Enable strobes.
During the second phase, these signals are the data bus for the transaction.
Data(31:0):
During write cycles, the bus contains the data to be stored and is driven
from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in
either a single data transaction or in a burst of four words, and places it
into the on-chip read buffer.
The byte lanes used during the transfer are a function of the datum size,
the memory port width, and the system byte-ordering.
Addr(3:0)
O
I(1)
Low Address (3:0) A 4-bit bus which indicates which word/halfword/byte is currently expected by the
processor. For 32-bit port widths, only Addr(3:2) is valid during the transfer; for 16-bit port widths, only
Addr(3:1) are valid; for 8-bit port widths, all of Addr(3:0) are valid. These address lines always contain
the address of the current datum to be transferred. In writes and single datum reads, the addresses initially
output the specific target address, and will increment if the size of the datum is wider than the target
memory port. For quad word reads, these outputs function as a counter starting at '0000', and
incrementing according to the width of the memory port.
During Reset, the Addr(3:0) pins act as Reset Configuration Mode bit inputs for the BootProm16,
BootProm8, ReservedHigh, and ExtAddrHold options.
The R3041 Addr(1:0) output pins are designated as the unconnected Rsvd(1:0) pins in the R3051 and
R3081.
Diag
O Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on-
chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:
Cached/Uncached:
During the phase in which the A/D bus presents address information, this
pin is an active high output which indicates whether or not the current
read is a result of a cache miss. The value of this pin at this time other
than in read cycles is undefined.
I/D: A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.
The R3041 Diag output pin is designated as the Diag(1) output pin in the R3051 and R3081.
ALE O Address Latch Enable: Used to indicate that the A/D bus contains valid address information for
the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.
DataEn
O
Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus
trans-
action is occurring, this signal is negated, thus disabling the external memory drivers.
NOTE:
1. Reset Configuration Mode bit input when Reset is asserted, normal signal
function when Reset is de-asserted.
2905 tbl 03
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| PDF Descargar | [ Datasheet IDT79RV3041.PDF ] | |
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