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PDF PC87413 Data sheet ( Hoja de datos )

Número de pieza PC87413
Descripción LPC ServerI/O for Servers and Workstations
Fabricantes National Semiconductor 
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No Preview Available ! PC87413 Hoja de datos, Descripción, Manual

July 2003
Revision 1.2
PC87413, PC87414, PC87416, PC87417
LPC ServerI/O for Servers and Workstations
General Description
The National Semiconductor® PC8741x family of LPC Serv-
erI/O devices (“PC8741x”) comprises highly integrated Ad-
vanced I/O products. The PC8741x is targeted for a wide
range of servers and workstations that use the Low Pin Count
(LPC) bus for the host interface and the serial ACCESS.bus
or SMBus® for the embedded controller interface.
The PC8741x features an X-Bus extension for read and write
operations over the X-Bus for both LPC and ACCESS.bus
cycles. Boot Flash and I/O devices can be accessed over this
X-Bus.
Embedded controllers can access the PC8741x and its X-Bus
via the ACCESS.bus or SMBus serial interface when VSB
exists, regardless of the LPC bus state. Some of the
PC8741x logical devices can be disabled, or their pins can be
floated, under control of the VSB-powered serial bus.
The PC8741x provides a VSB-powered high-frequency clock
for on-chip peripherals and for other VSB-powered platform
components.
The PC8741x’s extended wake-up support complements the
chipset’s ACPI controller and the platform embedded control-
lers. The PC8741x can monitor the Power and Sleep buttons
and control the power supply of simple platforms that lack an
embedded controller. The System Wake-Up Control (SWC)
module is powered by VSB and VBAT power supplies. It sup-
ports flexible wake-up and power-off request mechanisms in
any sleep state. It features Main and Standby power-on
elapsed-time counters.
The PC8741x also incorporates a Floppy Disk Controller
(FDC), two serial ports (UARTs), a Keyboard and Mouse
Controller (KBC), a Real-Time Clock (RTC), a fully compliant
IEEE 1284 Parallel Port, General-Purpose Input/Output
(GPIO) for a total of 51 ports and an Interrupt Serializer for
Parallel IRQs.
Outstanding Features
s LPC Interface, based on Intel’s LPC Interface Specifi-
cation, Revision 1.0, September 29th, 1997
s VSB-powered access to modules through ACCESS.bus
or SMBus (PC87413 and PC87417)
s X-Bus Extension for memory and I/O (PC87416 and
PC87417)
s PC01 Revision 0.5 and ACPI Revision 1.0b compliant
s ServerI/O modules: Parallel Port, FDC, two Serial Ports
(UARTs) and a Keyboard and Mouse Controller (KBC)
s Y2K-compliant RTC with 242 bytes of RAM
s 51 GPIO ports with a variety of wake-up events
s Extremely low current consumption in Battery Backup mode
s 128-pin PQFP package
Block Diagram
PC87417(See page 5 for other PC8741x diagrams.)
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Wake-Up Control
Power
On
Timers
RTC
Internal Clocks
Clock
GPIO
Generator Ports
X-Bus
Extension
Device
Configuration
ACCESS.bus
Interface
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O X-Bus XIRQ Clock Serial
32.768 KHz Clock Clock Ports Interface
Data
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other
brand or product names are trademarks or registered trademarks of their respective holders.
© 2003 National Semiconductor Corporation
www.national.com

1 page




PC87413 pdf
Features (Continued)
Block Diagrams
These are the block diagrams for the remaining PC8741x devices (see page 1 for the PC87417):
PC87413
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Wake-Up Control
Power
On
Timers
Internal Clocks
RTC
Clock
GPIO
Generator Ports
Device
Configuration
ACCESS.bus
Interface
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O
32.768 KHz Clock Clock Ports
Clock Serial
Data
PC87414
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Power
Wake-Up Control
On
Timers
Internal Clocks
RTC
Clock
GPIO
Generator Ports
Device
Configuration
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O
32.768 KHz Clock Clock Ports
PC87416
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Wake-Up Control
Power
On
Timers
RTC
Internal Clocks
Clock
GPIO
Generator Ports
X-Bus
Extension
Device
Configuration
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O X-Bus XIRQ
32.768 KHz Clock Clock Ports Interface
Revision 1.2
5 www.national.com

5 Page





PC87413 arduino
Table of Contents (Continued)
6.2.7
6.2.8
6.2.9
6.2.10
Arbitration on the Bus ................................................................................................ 120
Packet Error Check (PEC) ......................................................................................... 120
ACCESS.bus Protocol ............................................................................................... 121
Transaction Execution ............................................................................................... 125
6.3 ACB REGISTERS (ON ACCESS.BUS ONLY) ........................................................................ 126
6.3.1 ACB Register Map (on ACCESS.bus Only) .............................................................. 126
6.3.2 ACCESS.bus Control/Status Register (ACBCST) ..................................................... 127
6.3.3 ACCESS.bus Configuration Register (ACBCFG) ...................................................... 128
6.3.4 ACCESS.bus Lock Control Register (ACBLKCTL) ................................................... 128
6.3.5 ACCESS.bus Fast Disable Register (ACBFDIS) ....................................................... 130
6.3.6 ACCESS.bus TRI-STATE Register (ACBTRIS) ........................................................ 131
6.3.7 Access Lock Configuration 1 Register (ACCLCF1) ................................................... 132
6.3.8 Access Lock Configuration 2 Register (ACCLCF2) ................................................... 133
6.4 ACB REGISTER BITMAP ........................................................................................................ 134
7.0 General-Purpose Input/Output (GPIO) Ports
7.1 OVERVIEW ............................................................................................................................. 135
7.2 BASIC FUNCTIONALITY ........................................................................................................ 136
7.2.1 Configuration Options ................................................................................................ 136
7.2.2 Operation ................................................................................................................... 137
7.3 EVENT HANDLING AND SYSTEM NOTIFICATION .............................................................. 137
7.3.1 Event Configuration ................................................................................................... 137
7.3.2 System Notification .................................................................................................... 138
7.4 GPIO PORT REGISTERS ....................................................................................................... 139
7.4.1 GPIO Pin Configuration Registers Structure ............................................................. 139
7.4.2 GPIO Port Runtime Register Map ............................................................................. 140
7.4.3 GPIO Data Out Register (GPDO) .............................................................................. 140
7.4.4 GPIO Data In Register (GPDI) .................................................................................. 140
7.4.5 GPIO Event Enable Register (GPEVEN) .................................................................. 141
7.4.6 GPIO Event Status Register (GPEVST) .................................................................... 141
8.0 Real-Time Clock (RTC)
8.1 OVERVIEW ............................................................................................................................. 142
8.2 FUNCTIONAL DESCRIPTION ................................................................................................ 142
8.2.1 Bus Interface ............................................................................................................. 142
8.2.2 RTC Clock Generation .............................................................................................. 142
8.2.3 Internal Oscillator ....................................................................................................... 142
8.2.4 External Oscillator ..................................................................................................... 143
8.2.5 Timing Generation ..................................................................................................... 144
8.2.6 Timekeeping .............................................................................................................. 144
8.2.7 Updating .................................................................................................................... 145
8.2.8 Alarms ....................................................................................................................... 145
8.2.9 Power Supply ............................................................................................................ 146
8.2.10 System Bus Lockout .................................................................................................. 147
Revision 1.2
11 www.national.com

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