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PDF IDT77V106L200TFI Data sheet ( Hoja de datos )

Número de pieza IDT77V106L200TFI
Descripción 3.3V ATM PHY for 25.6 and 51.2 Mbps
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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3.3V ATM PHY
for 25.6 and 51.2 Mbps
IDT77V106L25
FEATURES:
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions of the
Physical Layer
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6Mbps physical interface
Also operates at 51.2Mbps data rate
8-bit UTOPIA Level 1 Interface
3-Cell Transmit & Receive FIFOs
Receiver Auto-Synchronization and Good Signal Indication
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
64-lead TQFP Package (10 x 10 mm)
Commercial and Industrial Temperature Ranges
DESCRIPTION:
The IDT77V106L25 is a member of IDT’s family of products supporting
Asynchronous Transfer Mode (ATM) data communications and networking.
The IDT77V106L25 implements the physical layer for 25.6 Mbps ATM,
connecting a serial copper link (UTP Category 3 and 5) to an ATM layer device
such as a SAR or a switch ASIC. The IDT77V106L25 also operates at 51.2
Mbps and is well suited to back-plane driving applications. The 77V106L25
utilizes an 8-bit UTOPIA interface on the cell side.
The IDT77V106L25 is fabricated using IDT’s state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
APPLICATIONS:
Up to 51.2Mbps backplane transmission
Rack-to-rack short links
ATM Switches
BLOCK DIAGRAM
TXREF
TXCLK
TXDATA
TXSOC
TXEN
TXCLAV
9
3 CELL FIFO
ALE
WR
RD
CS
AD[7:0]
INT
RESET
8
UTILITY
BUS
CONTROLLER
RXCLK
RXDATA
RXSOC
RXEN
RXCLAV
9
RXREF
3 CELL FIFO
TXLED
SCRAMBLER
PRNG
4B/5B
ENCODER
P/S
NRZI
Line
Driver
TXD+
TXD-
RESET
LOOP BACK
DESCRAMBLER
5B/4B
DECODER
S/P
DNRZI
RxLED
77V106
CLK
REC
Line
RXVR
RXD+
RXD-
OSC
77v106 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
JULY 2003
DSC-5360/3

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IDT77V106L200TFI pdf
IDT77V106L25
Functional Description
Transmission Convergence (TC) Sub Layer
Introduction
The TC sub layer defines the line coding, scrambling, data framing and
synchronization. Under control of a switch interface or Segmentation and
Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell,
scrambles the data, appends a command byte to the beginning of the cell, and
encodes the entire 53 bytes before transmission. These data transformations
ensure that the signal is evenly distributed across the frequency spectrum. In
addition, the serialized bit stream is NRZI coded. An 8kHz timing sync pulse
may be used for isochronous communications.
The PRNG is clocked every time a nibble is processed, regardless of
whether the processed nibble is part of a data or command byte. Note however
that only data nibbles are scrambled. The entire command byte (X _C) is NOT
scrambled before it’s encoded (see diagram for
illustration).
The PRNG is based upon the following polynomial:
X10 + X7 + 1
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
generated from the following equations:
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte is
distinguished by an escape symbol followed by one of 17 encoded symbols.
Together, this byte forms one of seventeen possible command bytes. Three
command bytes are defined:
1. X_X (read:‘escape’symbolfollowedbyanother‘escape’):Start-of-
cell with scrambler/descrambler reset.
2. X_4 (‘escape’ followed by ‘4’): Start-of-cell without scrambler/
descrambler reset.
3. X_8 (‘escape’ followed by ‘8’): 8kHz timing marker. This command
byte is generated when the 8kHz sync pulse is detected, and has
priority over all line activity (data or command bytes). It is transmitted
immediately when the sync pulse is detected. When this occurs
during a cell transmission, the data transfer is temporarily interrupted
on an octet boundary, and the X_8 command byte is inserted. This
condition is the only allowed interrupt in an otherwise contiguous
transfer.
Below is an illustration of the cell structure and command byte usage:
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell}...
In the above example, the first ATM cell is preceded by the X_X start-of-
cell command byte which resets both the transmitter-scrambler and receiver-
descrambler pseudo-random nibble generators (PRNG) to their initial states.
The following cell illustrates the insertion of a start-of-cell command without
scrambler/descrambler reset. During this cell’s transmission, an 8kHz timing
sync pulse triggers insertion of the X_8 8kHz timing marker command byte.
Transmission Description
Refer to Figure 2. Cell transmission begins with the PHY-ATM Interface.
An ATM layer device transfers a cell into the 77V106L25 across the Utopia
transmit bus. This cell enters a 3-cell deep transmit FIFO. Once a complete cell
is in the FIFO, transmission begins by passing the cell, four bits (MSB first) at
a time to the ‘Scrambler’.
The ‘Scrambler’ takes each nibble of data and exclusive-ORs them against
the 4 high order bits (X(t), X(t-1), X(t-3)) of a 10 bit pseudo-random nibble
generator (PRING). Its function is to provide the appropriate frequency
distribution for the signal across the line.
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1).
A scrambler lock between the transmitter and receiver occurs each time
an X_X command is sent. An X_X command is initiated only at the beginning
ofacelltransferafterthePRNGhascycledthroughallofitsstates(210 -1=1023
states). The first valid ATM data cell transmitted after power on will also be
accompanied with an X_X command byte. Each time an X_X command byte
is sent, the first nibble after the last escape (X) nibble is XOR’d with 1111b
(PRNG = 3FFx).
Because a timing marker command (X_8) may occur at any time, the
possibility of a reset PRNG start-of-cell command and a timing marker command
occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection
of the last two consecutive escape (X) nibbles will cause the PRNG to reset to
its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble
of the second consecutive escape pair.
Once the data nibbles have been scrambled using the PRNG, the nibbles
are further encoded using a 4b/5b process. The 4b/5b scheme ensures that
an appropriate number of signal transitions occur on the line. A total of
seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles
and the one escape (X) nibble. The table below lists the 4-bit data with their
corresponding 5-bit symbols:
Data
0000
0100
1000
1100
Symbol
10101
00111
10010
10111
Data
0010
0110
1010
1110
Symbol
01010
01110
11010
11110
Data
0001
0101
1001
1101
Symbol
01001
01101
11001
11101
Data
0011
0111
1011
1111
Symbol
01011
01111
11011
11111
ESC(X) = 00010
3505 drw 05a
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IDT77V106L200TFI arduino
IDT77V106L25
CONTROL AND STATUS INTERFACE
Utility Bus
The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V106. These registers are used to select desired operating
characteristics and functions, and to communicate status to external systems.
The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch Enable
(ALE) signal.
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms. A register read is performed as follows:
1. Initialcondition:
RD, WR, CS not asserted (logic 1)
— ALE not asserted (logic 0)
2. Set up register address:
— place desired register address on AD[7:0]
— set ALE to logic 1;
— latch this address by setting ALE to logic 0.
3. Read register data:
— Remove register address data from AD[7:0]
— assert CS by setting to logic 0;
— assert RD by setting to logic 0
— wait minimum pulse width time (see AC specifications)
Write Operation
A register write is performed as described below:
1. Initialcondition:
RD, WR, CS not asserted (logic 1)
— ALE not asserted (logic 0)
2. Set up register address:
— place desired register address on AD[7:0]
— set ALE to logic 1;
— latch this address by setting ALE to logic 0.
3. Writedata:
— place data on AD[7:0]
— assert CS by setting to logic 0;
— assert WR (logic 0) for minimum time (according to timing specification); reset WR or CS to logic 1 to complete register write cycle.
Interrupt Operations
A variety of selectable interrupt and signalling conditions are provided. They are useful both during ‘normal’ operation, and as diagnostic aids. Refer to
the Status and Control Register List section.
Overall interrupt control is provided via bit 0 of the Master Control Register. When this bit is cleared (set to 0), interrupt signalling is prevented. The Interrupt
Mask Register allows individual masking of different interrupt sources. Additional interrupt signal control is provided by bit 5 of the Master Control Register.
When this bit is set (=1), receive cell errors will be flagged via interrupt signalling and all other interrupt conditions are masked. These errors include:
Bad receive HEC
Short (fewer than 53 bytes) cells
Received cell symbol error
Normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the Master Control Register. INT (pin 34) will go to a low state when an
interrupt condition is detected. The external system should then interrogate the 77V106L25 to determine which one (or more) conditions caused this flag, and
reset the interrupt for further occurrences. This is accomplished by reading the Interrupt Status Register. Decoding the bits in this byte will tell which error condition
caused the interrupt. Reading this register also:
clears the (sticky) interrupt status bits in the registers that are read
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