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PDF IDT77155L155 Data sheet ( Hoja de datos )
| Número de pieza | IDT77155L155 | |
| Descripción | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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Integrated Device Technology, Inc.
PHY (TC-PMD) USER NETWORK
INTERFACE FOR 155 MBPS ATM
NETWORK APPLICATIONS
ADVANCED
INFORMATION
IDT77155
KEY FEATURES
• One chip ATM User Network Interface for 155.52 Mbps/
51.84Mbps operating speed.
• Full implementation of the SONET/SDH criteria according
to Bellcore GR-253-CORE and ITU-T G.709, G.783.
• Full implementation of the ATM physical layer according
to CCITT I.432 and ATM Forum User Network Interface
Specification.
• Full-duplex 155.52 Mbps STS-3c/STM-1 or 51.84 Mbps
STS-1 data with built-in clock/data recovery and clock
synthesis.
• Supports 4-cell PHY FIFO buffers for both transmit and
receive directions with parity.
• Provides GFC bits insertion and extraction.
• UTOPIA Level 1 and Level 2 Interface.
• Supports up to 4 PHYs for Multi-PHY connections with 2-
bit address and 8-bit data using UTOPIA 2 protocol.
• Provides an 8-bit microprocessor bus interface for
configuration, control and monitoring.
• Low power CMOS
• 128 pin PQFP Package (14 mm x 20 mm).
DESCRIPTION
The IDT77155 is a member of IDT's SWITCHStAR™ family
of products for Asynchronous Transfer Mode (ATM) net-
works.
The IDT77155 is a integrated circuit that provides the
SONET/SDH processing and ATM mapping functions of a
155 Mbps/51 Mbps ATM User Network Interface. Provides full
compliance with SONET/SDH requirements and ATM Forum
SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM
TFCLK
TXPRTY
TDAT[7:0]
TSOC
TCA
TxADDR[1:0]
MPHYEN
RxADDR[1:0]
TSEN
RFCLK
RXPRTY
RDAT[7:0]
RSOC
RCA
TUrTACFTFaCrIOTIenFaFeMlsPnlOOlmlsIAmit it
Transmit
SONET
Framer
Receive
UTOPIA
Cell
FIFO
Receive
SONET
Framer
Micoprocessor
Interface
NICStAR is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
8.03
Clk Gen.
Parallel
to
Serial
EEnnccooddeerr
Serial
to
Parallel
Decoder
CClklkRRece.c.
TRCLK-
TRCLK+
TXC-
TXC+
TXD+
TXD-
RXDO-
RXD-
RXD+
RXDO+
RRCLK-
RRCLK+
ALOS-
ALOS+
3497 drw 01
NOVEMBER 1996
DSC-2066/5
1
1 page  
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
PIN DESCRIPTIONS (CONTINUED)
Symbol
RBYP
RCA/
RXEMPTY
RCLK
RCP
RD
RDAT0-
RDAT7
RFCLK
RFP
RGFC
RRCLK+
RRCLK-
RRDENB
Name
I/O
Receive Bypass I
Receive Cell
Available
O
Receive Clock O
Receive Cell
O
Read
I
Receive Data O
Receive FIFO
Clock
I
Receive Frame O
Pulse
Receive Generic O
Flow Control
Receive Differential I
Reference Clock
Receive Read
Enable
I
Description
Active high RBYP input disables clock recovery. If enabled, the receive different serial data
RXD+/- is sampled on the rising edged of the receive differential reference clock RRCLK+/-.
If RBYP is disabled, the receive clocks are recovered from RXD+/- bit stream. RBYP has an
integral pull down resistor.
Pin #: 41
This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the
tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the
polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is
tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy
protocol.
Pin #: 69
Provides a timing reference, and is a divide-by-8 version of tri-covered clock when RBYP is
disabled or RRCLK+/- when RBYP is enabled.
Pin #: 57
Receive GFC pulse indicates the start of the four generic flow control bits (GFC) in the
RGFC Pulse output. RCP is coincident with the most significant GFC bits. RCP is updated
on the rising edge of RCLK.
Pin #: 60
Active low read signal to read contents of addressed register. The data bus is driven by the
contents of the addresses register when the read signal is asserted along with the chip
select (CS) signal.
Pin #: 105
The receive cell data to the ATM layer from the receive FIFO. This is updated on the rising
edge of RFCLK. RDAT[7:0] is tristated if TSEN is asserted or if MPHYEN is asserted. In
UTOPIA single-phy mode, it is driven if RRDENB is asserted (TSEN also asserted) or
always driven if TSEN is low. In UTOPIA multi-phy mode, RDAT[7:0] is driven following the
level-2 protocol.
Pin #: RDAT0/70, RDAT1/71, RDAT2/74, RDAT3/75, RDAT4/76, RDAT5/77, RDAT6/78,
RDAT7/79
The receive ATM clock from the ATM layer <= 40 MHz. The start of cell indication, the
transmit data, and the transmit data parity signals are updated on the rising edge of this
clock. RRDENB is sampled on the rising edge of this clock.
Pin #: 67
An 8 KHz signal synchronized to RCLK. It is pulse high for one clock every 2430 RCLK
cycles for STS-3c or every 810 RCLK cycles for STS-1. It is updated on the rising edge of
RCLK.
Pin #: 58
Outputs the extracted generic flow control bits (GFC) in a serial stream. The four GFC bits
are output for each receive cell, and the first of the four bits is coincident with the RCP
output, RGFC is low until cell delineation is achieved. RGFC is updated on the rising edge of
RCLK.
Pin #: 59
Inputs contain a jitter-free 19.44 MHz or a 6.48 MHz reference clock when clock recovery
is enabled (RBYP = 0). When RBYP is enabled, RRCLK+/- is nominally a 155.52 MHz or
51.84 MHz 50% duty cycle clock and provides the timing for the internal receive functions.
RXD+/- is sampled on the rising edge of RRCLK+/-
Pin #: RRCLK+/34/ RRCLK-/33
Active low signal from ATM signifying that data will be sampled on RDAT[7:0] in the
following clock cycle. When sampled high, RSOC and RDAT[7:0] are tristated, if TSEN is
enabled. RRDENB must operate with RFCLK at high rate to prevent receive FIFO overflow
and loss of receive data.
Pin #: 68
8.03 5
5 Page 
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
of any pattern other than “111” in bits 6-8 of K2 byte are
detected.
For SDH applications, Line AIS is declared when three
consecutive frames “111” pattern in bits 6-8 of K2 byte are
detected. Line AIS is removed when three consecutive
frames of any pattern other than “111” in bits 6-8 of K2 byte
are detected. The selection of SONET or SDH detection
criteria is set by control register.
The Line Remote Defect Indication (RDI) is detected in the
incoming data stream. Line RDI is declared when five con-
secutive frames of “110” pattern in bits 6-8 of K2 byte are
detected. Line RDI is removed when five consecutive frames
of any pattern other than “110” in bits 6-8 of K2 byte are
detected.
For SDH applications, Line RDI is declared when three
consecutive frames of “110” pattern in bits 6-8 of K2 byte are
detected. Line RDI is removed when three consecutive
frames of any pattern other than “110” in bits 6-8 of K2 byte
are detected. The selection of SONET or SDH detection
criteria is set by control register.
K1 and K2 bytes are extracted if new identical values are
received for 3 consecutive frames for Automatic Switch
Protection (APS) use.
The Line Far End Block Error (LFEBE) can be monitored
by extracting the 8-bit FEBE from the incoming third Z2 byte.
the error count range is from 0 to 24 errors. Any other value
is counted as zero error. Up to 192,000 (24x 8000) bit errors
can be detected for one second,
One 20-bit saturating counter is provided to accumulate
these FEBE errors. This counter is to be read and reset via
microprocessor interface.
The Pointer Interpreter interprets the incoming pointer
byte (H1, H2) to determine the location of the J1 byte (path
overhead) in the incoming STS-3c or STS-1 data stream.
The Pointer Interpreter detects loss of pointer (LOP) and
path AIS in the incoming STS-3c or STS-1 data stream.
LOP is declared when eight consecutive invalid pointers
or eight consecutive NDF enabled indications are detected.
LOP is removed when three consecutive same valid pointers
with normal NDF are detected.
Path AIS is declared when three consecutive “all-one”
pattern in H1 and H2 byte are detected. Path AIS is removed
when three consecutive same valid pointers with normal
NDF are detected or when a valid pointer with NDF enabled
is detected.
The B3 BER is monitored by the incoming Path BIP-8
error detection code (B3). The BIP-8 code is calculated over
all bits of the synchronous payload envelope after
descrambling by bit interleaved parity calculation using even
parity. And obtains errors by comparing the calculated BIP-
8 code with the BIP-8 code extracted from the B3 byte of the
next incoming frame. Up to 64,000 (8 x 8000) bit errors can be
detected for one second.
One 16-bit saturating counter is provided to accumulate
these BIP errors. This counter is to be read via microproces-
sor interface at least once per second for performance moni-
toring.
C2 Mismatch is detected in the incoming data stream. C2
Mismatch is declared when five consecutive frames of the
value other than “13h” in C2 byte are detected. C2 Mismatch
is removed when five consecutive frames of the value “13h”
in C2 byte are detected.
The Path Far End Block Error (PFEBE) can be monitored
by extracting the 4-bit FEBE from the incoming path status
byte (G1). the error count range is from “0000” to “1000” to
represent zero to eight errors. Any other value is counted as
zero error. Up to 64,000 (8 x 8000) bit errors can be detected
for one second,
One 16-bit saturating counter is provided to accumulate
these FEBE errors. This counter is to be read and reset via
microprocessor interface.
Path Remote Defect Indication (RDI-P) is detected by
checking the bit 5 of path status byte (G1) in the incoming data
stream. Path RDI is declared when ten consecutive frames of
value “1” in bit 5 of G1 byte are detected. Path RDI is removed
when ten consecutive frames of value “0” in bit 5 of G1 byte
are detected.
RECEIVE UTOPIA CELL FIFO
The Receive UTOPIA Cell FIFO provides functions for
ATM cell delineation, HEC error verification, cell filtering, and
ATM cell payload descrambling. This block also provides a
four cell deep receive FIFO.
Cell Delineation is for validating the HEC of a cell header
by checking with the CRC-8 calculation over first 4 bytes of
ATM cell header; the coset value of “55h” can be optionally
added to the HEC during validation. HEC validation uses the
state machine in CCITT recommendation I.432 and is shown
in Figure 1.
The state machine shown in Figure 1 is initialized to the
HUNT state in which every byte of ATM 53 byte is checked
for a valid HEC. Once correct HEC has been found, cell
delineation state machine enters the PRESYNC state that
validates HEC on a cell by cell basis. If additional DELTA
(value is suggested to be six) consecutive correct HECs are
validated, the state machine enters the SYNC state. How-
ever, if any incorrect HEC is found in the PRESYNC state, the
state machine reverts to HUNT state. Once in SYNC state, it
stays in the SYNC state until ALPHA (value is suggested to be
seven) consecutive incorrect HECs are detected. HUNT state
is entered and the search for a correct HEC on a byte by byte
basis resumes.
Cell could be discarded with HEC errors by using HEC
8.03 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT77155L155.PDF ] | |
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