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PDF PC87391-VJG Data sheet ( Hoja de datos )

Número de pieza PC87391-VJG
Descripción 100-Pin LPC SuperI/O Devices for Portable Applications
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! PC87391-VJG Hoja de datos, Descripción, Manual

PRELIMINARY
September 2000
Revision 1.41
PC87391, PC87392, PC87393, PC87393F
100-Pin LPC SuperI/O Devices for Portable Applications
General Description
National Semiconductor’s PC8739x family of LPC SuperI/O
devices is targeted for a wide range of portable applications.
PC99 and ACPI compliant, the PC8739x family features
an X-Bus Extension for read and write operations over the
X-Bus, a full IEEE 1284 Parallel Port with a Parallel Port Mul-
tiplexer (PPM) for external Floppy Disk Drive (FDD) support,
a Musical Instrument Digital Interface (MIDI) port, and a
Game port. Like all National LPC SuperI/O devices, the
PC8739x offers a single-chip solution to the most commonly
used PC I/O peripherals.
The PC8739x family also incorporates: a Floppy Disk Con-
troller (FDC), two enhanced Serial Ports (UARTs), one with
Fast Infrared (FIR, IrDA 1.1 compliant), General-Purpose
Input/Output (GPIO) support for a total of 32 ports, Interrupt
Serializer for Parallel IRQs and an enhanced WATCH-
DOGtimer.
The following features apply to the PC87393F. The feature
lists for other PC8739x devices may differ. See the table on
page 3 for a list of features for each device.
Outstanding Features
q X-Bus Extension for read and write operations
q LPC bus interface, based on Intel’s LPC Interface Spec-
ification Rev. 1.01, February 1999 (supports CLKRUN
and LPCPD signals) and Intel FWH transactions
q PC99 and ACPI compliant
q Serial IRQ support (15 options)
q Interrupt Serializer (four Parallel IRQs to Serial IRQ)
q PPM for external FDD signal support
q MIDI interface compatible with MPU-401 UART mode
q Game port inputs for up to two joysticks
q Protection features, including GPIO lock and pin con-
figuration lock
q 32 GPIO ports (16 standard, 16 with Assert IRQ/SMI)
q 5V tolerant and back-drive protected pins (except LPC
bus pins)
q 100-pin TQFP Package
Block Diagram
PC87393 / PC87393F
Parallel Port\
Floppy Drive Interface
Serial Serial Infrared
Interface Interface Interface
I/O Floppy Drive
Ports Interface
PPM
LPC Serial
Parallel
Interface IRQ SMI IRQs
Serial Port 1
Serial Port 2
with FIR
GPIO Ports
Floppy Disk IEEE 1284
Controller Parallel Port
Bus
Interface
Interrupt
Serializer
VDD Wake-Up
Control
PWUREQ
WATCHDOG
Timer
X-Bus
Extension
Game Port
WDO
X-Bus Interface Game Device
Interface
MIDI Port
MIDI
Interface
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
©2000 National Semiconductor Corporation
www.national.com

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PC87391-VJG pdf
Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS ...................................................................................................... 11
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 15
1.3 PIN MULTIPLEXING ................................................................................................................. 15
1.4 PARALLEL PORT MULTIPLEXER (PPM) ................................................................................ 17
1.5 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 18
1.5.1 Bus Interface ............................................................................................................... 18
1.5.2 Clock ............................................................................................................................ 18
1.5.3 Infrared (IR) ................................................................................................................ 18
1.5.4 Floppy Disk Controller (FDC) ..................................................................................... 19
1.5.5 Game Port (PC87393 and PC87393F) ....................................................................... 20
1.5.6 General-Purpose Input/Output (GPIO) Ports (PC87392, PC87393 and PC87393F) 20
1.5.7 Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F) ............ 20
1.5.8 Parallel Port ................................................................................................................ 21
1.5.9 Power and Ground ..................................................................................................... 21
1.5.10 Serial Port 1 and Serial Port 2 (SP1 and SP2) ............................................................ 22
1.5.11 Strap Configuration ...................................................................................................... 23
1.5.12 Wake-Up Control ......................................................................................................... 23
1.5.13 WATCHDOG Timer ..................................................................................................... 23
1.5.14 X-Bus Extension (PC87393 and PC87393F) ............................................................. 23
1.6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 24
2.0 Device Architecture and Configuration
2.1 OVERVIEW ............................................................................................................................... 26
2.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 26
2.2.1 The Index-Data Register Pair ...................................................................................... 26
2.2.2 Banked Logical Device Registers Structure ................................................................ 28
2.2.3 Standard Logical Device Configuration Register Definitions ....................................... 29
2.2.4 Standard Configuration Registers ............................................................................... 31
2.2.5 Default Configuration Setup ........................................................................................ 32
2.2.6 Power States ............................................................................................................... 32
2.2.7 Address Decoding ....................................................................................................... 32
2.3 THE CLOCK MULTIPLIER ........................................................................................................ 33
2.3.1 Functionality ................................................................................................................ 33
2.3.2 Chip Power-Up ............................................................................................................ 33
2.3.3 Disabling the Clock ...................................................................................................... 33
2.3.4 Specifications .............................................................................................................. 33
2.4 INTERRUPT SERIALIZER ........................................................................................................ 34
2.5 WAKE-UP CONTROL ............................................................................................................... 34
2.6 THE PARALLEL PORT MULTIPLEXER (PPM) ........................................................................ 34
2.6.1 PPM Power Save Mode .............................................................................................. 35
2.7 PROTECTION ........................................................................................................................... 36
2.7.1 Pin Configuration Lock ................................................................................................ 36
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PC87391-VJG arduino
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAMS
SIN2
RTS2
SOUT2
CTS2
DTR2_BOUT2
RI2
NC
NC
MTR1
NC
NC
NC
VDD
VSS
(XCNF2) NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76 50
77 49
78 48
79 47
80 46
81 45
82 44
83 43
84 42
85 41
86 40
87 39
88 PC87391-VJG 38
89 37
90 36
91 35
92 34
93 33
94 32
95 31
96 30
97 29
98 28
99 27
100 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PD1/TRK0
INIT/DIR
PD2/WP
SLIN_ASTRB/STEP
PD3/RDATA
PD4/DSKCHG
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
ACK/DR1
BUSY_WAIT/MTR1
VDD
VSS
PE/WDATA
SLCT/WGATE
PNF
DRATE0/IRSL2
DENSEL
INDEX
MTR0
DR0
DIR
STEP
WDATA
WGATE
NC - Not Connected (these pins should be left unconnected)
Thin Quad Flatpack (TQFP), JEDEC
Order Number PC87391-VJG
See NS Package Number VLJ100A
www.national.com
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