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PDF PC87382-VBH Data sheet ( Hoja de datos )
| Número de pieza | PC87382-VBH | |
| Descripción | LPC-to-LPC Switch for Docking Stations/ with Fast Infrared Port/ Serial Port and GPIOs | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 2003
Revision 1.2
PC87382
LPC-to-LPC Switch for Docking Stations, with Fast
Infrared Port, Serial Port and GPIOs
General Description
The PC87382, a member of the National Semiconductor LPC
SuperI/O family, is targeted for a wide range of portable ap-
plications. The PC87382 is PC2001 and ACPI compliant, and
features an LPC-to-LPC Switch with hot plugability, Fast In-
frared port (FIR, IrDA 1.1 compliant), Serial Port, and Gener-
al-Purpose Input/Output (GPIO) support for a total of eight
ports.
The PC87382 enables glueless implementation of an LPC-
to-LPC Switch between the motherboard LPC bus and the
Docking Station, and supports hot insertion and hot removal.
Outstanding Features
q LPC-to-LPC Switch with hot plugability, enables LPC
devices in the Docking Station to be connected to the
Main LPC Bus, thus reducing the number of signals re-
quired through the Docking Station connector
q LPC bus interface, based on Intel’s LPC Interface
Specification Revision 1.1, August 2002 (supports
CLKRUN signal)
q Fast Infrared port
q PC2001 and ACPI Revision 2.0 compliant
q Serial IRQ support (15 options)
q Protection features, including GPIO lock and pin con-
figuration lock
q Eight GPIO ports, including with “assert IRQ” capability
q XOR Tree and TRI-STATE device pins (or ICT) test-
ability modes.
q 5V tolerant and back-drive protected pins (except LPC
bus pins)
q 48-pin LQFP package
System Block Diagram
LPC Bus
South Bridge
TPM
Embedded
Controller
I/O
Ports
Portable
Platform
Docking
Station
PC87382
Serial Infrared
Interface Interface
Docking LPC Bus
DCLKOUT
Docking
SIO
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
©2003 National Semiconductor Corporation
www.national.com
1 page  
Table of Contents (Continued)
3.3.2 Floating Module Output ............................................................................................... 24
3.4 INTERNAL ADDRESS DECODING .......................................................................................... 25
3.5 PROTECTION ........................................................................................................................... 25
3.5.1 Configuration Lock ....................................................................................................... 25
3.5.2 GPIO Ports Configuration Lock ................................................................................... 25
3.5.3 Fast Disable Configuration Lock .................................................................................. 25
3.5.4 Clock Control Lock ...................................................................................................... 25
3.5.5 GPIO Ports Lock .......................................................................................................... 25
3.6 REGISTER TYPE ABBREVIATIONS ........................................................................................ 26
3.7 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 26
3.7.1 SuperI/O ID Register (SID) .......................................................................................... 26
3.7.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 27
3.7.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 27
3.7.4 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 28
3.7.5 SuperI/O Revision ID Register (SRID) ........................................................................ 28
3.7.6 Clock Generator Control Register (CLOCKCF) ........................................................... 29
3.8 INFRARED CONFIGURATION ................................................................................................. 30
3.8.1 Logical Device 2 (IR) Configuration ............................................................................. 30
3.8.2 Infrared Configuration Register ................................................................................... 30
3.9 SERIAL PORT 1 CONFIGURATION ......................................................................................... 31
3.9.1 Logical Device 3 (SP1) Configuration .......................................................................... 31
3.9.2 Serial Port 1 Configuration Register ............................................................................ 31
3.10 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 32
3.10.1 General Description ..................................................................................................... 32
3.10.2 Implementation ............................................................................................................ 32
3.10.3 Logical Device 7 (GPIO) Configuration ....................................................................... 33
3.10.4 GPIO Pin Select Register (GPSEL) ............................................................................. 34
3.10.5 GPIO Pin Configuration Register (GPCFG) ................................................................ 34
3.10.6 GPIO Event Routing Register (GPEVR) ...................................................................... 35
3.11 DOCKING LPC SWITCH CONFIGURATION ............................................................................ 36
3.11.1 Logical Device 19 (DLPC) Configuration ..................................................................... 36
4.0 LPC Bus Interface
4.1 OVERVIEW ............................................................................................................................... 37
4.2 LPC TRANSACTIONS ............................................................................................................... 37
4.3 CLKRUN FUNCTIONALITY ...................................................................................................... 37
4.4 INTERRUPT SERIALIZER ........................................................................................................ 37
5.0 General-Purpose Input/Output (GPIO) Port
5.1 OVERVIEW ............................................................................................................................... 38
5.2 BASIC FUNCTIONALITY .......................................................................................................... 39
5.2.1 Configuration Options .................................................................................................. 39
5.2.2 Operation ..................................................................................................................... 39
Revision 1.2
5 www.national.com
5 Page 
1.0 Signal/Pin Connection and Description (Continued)
1.3.4 Infrared (IR)
Signal Pin(s) I/O Buffer Type
Description
IRRX1
5
IRRX2_IRSL0 7
IRTX
6
I INTS IR Receive 1. Primary input to receive serial data from the IR transceiver.
I/O INTS/O3/6 IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a second
transceiver.
IRSL0 - IR Select. Output used to control the IR transceiver.
O O6/12 IR Transmit. IR serial output data.
1.3.5 Serial Port (SP1)
Signal
Pin(s) I/O Buffer Type
Description
CTS1
1
DCD1
44
DSR1
45
DTR1_BOUT1 2
RI1
RTS1
3
47
SIN1
SOUT1
46
48
I
INTS
Clear to Send. When low, indicates that the modem or other data transfer
device is ready to exchange data.
I
INTS
Data Carrier Detected. When low, indicates that the modem or other data
transfer device has detected the data carrier.
I
INTS
Data Set Ready. When low, indicates that the data transfer device, e.g.,
modem, is ready to establish a communications link.
O O3/6 Data Terminal Ready. When low, indicates to the modem or other data
transfer device that the UART is ready to establish a communications link.
Baud Output. Provides the associated serial channel baud rate generator
output signal if Test Mode is selected, i.e., if bit 7 of the EXCR1 register is
set.
I
INTS
Ring Indicator. When low, indicates that a telephone ring signal was
received by the modem. It is monitored during power-off for wake-up event
detection.
O O3/6 Request to Send. When low, indicates to the modem or other data
transfer device that the corresponding UART is ready to exchange data. A
system reset sets this signal to inactive high; a loopback operation holds it
inactive.
I
INTS
Serial Input. Receives composite serial data from the communications link
(peripheral device, modem or other data transfer device).
O O3/6 Serial Output. Sends composite serial data to the communications link
(peripheral device, modem or other data transfer device). These signals
are set active high after a system reset.
1.3.6 General-Purpose Input/Output (GPIO) Ports
Signal
GPIO00-04
Pin(s)
11, 12,
13, 14,
15
GPIO20-21, 17, 21
GPIO23
22
I/O Buffer Type
Description
I/O
INTS/
General-Purpose I/O Port 0, bits 0-4. Each pin is configured independent-
OD6, O3/6
ly as input or I/O, with or without static pull-up, and with either open-drain or
push-pull output type. The port supports interrupt assertion, and each pin
can be enabled or masked as an interrupt source.
I/O
INTS/
General-Purpose I/O Port 2, bits 0,1,3. Same as Port 0, without
OD6, O3/6 interrupt support.
Revision 1.2
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