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PDF IDT74FST163P245 Data sheet ( Hoja de datos )

Número de pieza IDT74FST163P245
Descripción 16-BIT BUS SWITCH
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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16-BIT BUS SWITCH
IDT74FST163245
IDT74FST163P245
ADVANCE INFORMATION
Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 5
FST163Pxxx – 5with precharge
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163245/163P245 belong to IDT's family of Bus
switches. Bus switch devices perform the function of connect-
ing or isolating two ports without providing any inherent
current sink or source capability. Thus they generate little or
no noise of their own while providing a low resistance path for
an external driver. These devices connect input and output
ports through an n-channel FET. When the gate-to-source
junction of this FET is adequately forward-biased the device
conducts and the resistance between input and output ports
is small. Without adequate bias on the gate-to-source junction
of the FET, the FET is turned off, therefore with no VCC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163245 and FST163P245 are 16-bit TTL-compat-
ible bus switches. The OE pins provide enable control. The
FST163P245 supports precharge on the B port. So when OE
is high, A and B ports are isolated and B outputs are precharged
to the bias voltage through the equivalent of a 10Kresistor
(1B1-8 precharged to VBIAS1 and 2B1-8 precharged to VBIAS1).
FUNCTIONAL BLOCK DIAGRAM
VBIAS1
1A1
1A1 1B1
1A8
1A8 1B8
1B1
1B8
VBIAS1
2A1 2B1 2A1
2B1
2A8 2B8
1OE
2OE
FST163245
PIN DESCRIPTION
Pin Names
1A1-8, 2A1-8
I/O Description
I/O Bus A
1B1-8, 2B1-8
1OE, 2OE
I/O Bus B
I Bus Switch Enable (Active LOW)
VBIAS1
I Precharge Reference Voltage
3513 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
1
2A8
1OE
2OE
2B8
FST163P245
3513 drw 01
FEBRUARY 1997
DSC-3513/-

1 page




IDT74FST163P245 pdf
IDT74FST163245, IDTFST163P245
16-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
V OUT
50pF
CL
500
500
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3513 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3513 lnk 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
tSU tH
3V
1.5V
0V
3V
LOW-HIGH-LOW
PULSE
1.5V
INPUT
ASYNCHRONOUS CONTROL
PRESET
tREM
1.5V
0V
3V
tW
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
tH
3V
1.5V
0V
3513 lnk 05
ETC.
3513 lnk 04
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3513 lnk 06
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
NOTES:
3513 lnk 07
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
5

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