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PDF IDT74FST163244 Data sheet ( Hoja de datos )

Número de pieza IDT74FST163244
Descripción 16-BIT BUS SWITCH
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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16-BIT BUS SWITCH
IDT74FST163244
ADVANCE INFORMATION
Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 7
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
• Pin-compatible with FCT16244/FCT162244T
FUNCTIONAL BLOCK DIAGRAM
1OE
1A1
1A2
1A3
1A4
1B1
1B2
1B3
1B4
DESCRIPTION:
The FST163244 belongs to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
their own while providing a low resistance path for an external
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. With-
out adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
3OE
3A1
3A2
3A3
3A4
3B1
3B2
3B3
3B4
2OE
2A1
2A2
2A3
2A4
2B1
2B2
2B3
2B4
PIN DESCRIPTION
Pin Names
XOE
XAx
XBx
Description
Output Enable Inputs (Active LOW)
A Port Bits
B Port Bits
3615 tbl 01
4OE
4A1
4A2
4A3
4A4
4B1
4B2
4B3
4B4
3615 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
1
FEBRUARY 1997
DSC-3615/-

1 page




IDT74FST163244 pdf
IDT74FST163244
16-BIT BUS SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
VIN
Pulse
Generator
D.U.T.
RT
V OUT
50pF
CL
500
500
SWITCH POSITION
Test
Switch
7.0V
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3615 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
3615 lnk 03
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3615 lnk 04
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
ENABLE AND DISABLE TIMES
1.5V
1.5V
3615 lnk 05
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3615 lnk 06
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
tPLZ
3.5V
3.5V
1.5V
tPHZ
0.3V VOL
1.5V
0.3V VOH
0V 0V
NOTES:
3615 lnk 07
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
5

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