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PDF IDT74FST163233PA Data sheet ( Hoja de datos )
| Número de pieza | IDT74FST163233PA | |
| Descripción | 16-BIT 2:1 MUX/DEMUX SWITCH | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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16-BIT 2:1 MUX/DEMUX
SWITCH
IDT74FST163233
ADVANCE INFORMATION
Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 7Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163233 belongs to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
their own while providing a low resistance path for an external
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. With-
out adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163233 provides three 16-bit TTL-compatible
ports that support 2:1 multiplexing. The SEL0,1 and TEST0,1
pins provide switch enable and mux select control as shown
below.
The A port can be connected to port 1B or port 2B or both
ports 1B and 2B.
FUNCTIONAL BLOCK DIAGRAM
SEL0
TEST0
SEL1
TEST1
0A1-8
One of Eight
Channels
2B1-8
1B1-8
1A9-16
One of Eight
Channels
2B9-16
1B9-16
3512 drw 01
PIN DESCRIPTION
Pin Names
A, 1B, 2B
I/O
I/O
SEL0-1,
TEST0-1
I
Description
Buses A, 1B, 2B
Control Pins for Mux and Switch
Enable Functions
3512 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
1
AUGUST 1996
DSC-3512/1
1 page  
IDT74FST163233
16-BIT MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500Ω
500Ω
7.0V
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3512 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3512 lnk 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
tSU tH
3V
1.5V
0V
3V
LOW-HIGH-LOW
PULSE
1.5V
INPUT
ASYNCHRONOUS CONTROL
PRESET
tREM
1.5V
0V
3V
tW
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
tH
3V
1.5V
0V
3512 lnk 05
ETC.
3512 lnk 04
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3512 lnk 06
ENABLE
DISABLE
3V
CONTROL
INPUT
tPZL
1.5V
0V
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
3.5V
1.5V
tPHZ
3.5V
0.3V VOL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0.3V VOH
0V
3512 lnk 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74FST163233PA.PDF ] | |
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