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Número de pieza IDT74FCT88915TT133PYB
Descripción LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
IDT54/74FCT88915TT
55/70/100/133
PRELIMINARY
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• TTL level output voltage swing
• 64/–15mA drive at TTL output voltage levels
• Available in 28 pin PLCC, LCC and SSOP packages
DESCRIPTION:
The IDT54/74FCT88915TT uses phase-lock loop technol-
ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
is fed back to the PLL at the FEEDBACK input resulting in
essentially delay across the device. The PLL consists of the
phase/frequency detector, charge pump, loop filter and VCO.
The VCO is designed for a 2Q operating frequency range of
40MHz to f2Q Max.
The IDT54/74FCT88915TT provides 8 outputs with 500ps
skew. The Q5 output is inverted from the Q outputs. The 2Q
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
The FREQ_SEL control provides an additional ÷ 2 option in
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RST is low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.
The IDT54/74FCT88915TT requires one external loop
filter component as recommended in Figure 1.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
LOCK
SYNC (0)
SYNC (1)
REF_SEL
PLL_EN
0M
u
1x
FREQ_SEL
OE/RST
Phase/Freq.
Detector
Charge Pump
01
Mux
Divide
-By-2
(÷1)
(÷2)
1M
u
0x
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
9.7
9.7
Voltage
Controlled
Oscilator
DQ
CP R Q
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
LF
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
3072 drw 01
AUGUST 1995
DSC-4247/1
11

1 page




IDT74FCT88915TT133PYB pdf
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
tRISE/FALL
All outputs
tPULSE WIDTH (3)
All outputs(3)
Parameter
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2, 2Q @ 1.5V
Condition(1)
Load = 50to
VCC/2, CL = 20pF
Min.
0.2(2)
0.5tCYCLE – 0.5(5)
Max.
1.2
0.5tCYCLE + 0.5(5)
Unit
ns
ns
tPD SYNC input to FEEDBACK delay
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK
input pins)
Load = 50to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND(9)
–0.5
+0.5 ns
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Load = 50to
VCC/2, CL = 20pF
350 ps
tSKEWf
(falling)(3,4)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
— 350 ps
tSKEWall (3,4)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
— 500 ps
tLOCK (6)
Time required to acquire
1(2) 10 ms
Phase-Lock from time
SYNC input signal is received
tPZH Output Enable Time
tPZL OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
3(2) 14 ns
tPHZ Output Disable Time
3(2) 14 ns
tPLZ OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
GENERAL AC SPECIFICATION NOTES:
3072 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions, and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF.
(Where C1 is loop filter capacitor shown in Figure 1).
9.7 5

5 Page





IDT74FCT88915TT133PYB arduino
IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER
ORDERING INFORMATION
IDT XX FCT XXXX
Temp. Range
Device Type
X
Speed
XX
Package Process
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Blank
B
J
PY
L
55
70
100
133
Commercial
MIL-STD-883, Class B
PLCC
SSOP
LCC
55MHz Max. frequency
70MHz Max. frequency
100MHz Max. frequency
133MHz Max. frequency
88915TT Low skew PLL-based CMOS clock driver
54 –55°C to +125°C
74 0°C to +70°C
3072 drw 15
9.7 11

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