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PDF IDT74FCT841A Data sheet ( Hoja de datos )

Número de pieza IDT74FCT841A
Descripción HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
Fabricantes Integrated Device 
Logotipo Integrated Device Logotipo



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®
Integrated Device Technology, Inc.
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
IDT54/74FCT841A/B/C
FEATURES:
• Equivalent to AMD’s Am29841-46 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT841A equivalent to FASTspeed
• IDT54/74FCT841B 25% faster than FAST
• IDT54/74FCT841C 40% faster than FAST
• Buffered common latch enable, clear and preset inputs
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular ‘373 function.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-imped-
ance state.
FUNCTIONAL BLOCK DIAGRAM
PRE
D0
CLR
DP
LE Q
CLR
LE
DN
DP
LE Q
CLR
OE
Y0 YN
2607 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology, Inc.
7.22
APRIL 1994
DSC-4603/2
1

1 page




IDT74FCT841A pdf
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A
FCT841B
FCT841C
Com'l. Mil. Com'l. Mil. Com'l. Mil.
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
Parameter
Propagation Delay
DI to YI (LE = HIGH)
Propagation Delay
LE to YI
Propagation Delay, PRE to YI
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
CL = 50pF
1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns
RL = 500
CL = 300pF(4) 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0
RL = 500
CL = 50pF 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns
RL = 500
CL = 300pF(4) 1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0
RL = 500
CL = 50pF 1.5 12.0 1.5 14.0 1.5 8.0 1.5 10.0 1.5 7.0 1.5 9.0 ns
tPHL RL = 5001.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 9.0 1.5 12.0
tPHL Propagation Delay, CLR to YI
1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 9.0 1.5 10.0 ns
tPLH 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5 9.0 1.5 9.0
tPZH Output Enable Time OE to YI CL = 50pF 1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 ns
tPZL RL = 500
CL = 300pF(4) 1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0
RL = 500
tPHZ Output Disable Time OE to Y I CL = 5pF(4) 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 ns
tPLZ RL = 500
CL = 50pF 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3
RL = 500
tSU
Data to LE Set-up Time
CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tH Data to LE Hold Time RL = 5002.5 — 3.0 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tW
LE Pulse Width(3)
HIGH
4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tW
PRE Pulse Width(3)
LOW
5.0 — 7.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tW
CLR Pulse Width(3)
LOW
4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tREM
Recovery Time PRE to LE
4.0 — 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns
tREM
Recovery Time CLR to LE
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
2607 tbl 07
7.22 5

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