DataSheet.es    


PDF PC87311A Data sheet ( Hoja de datos )

Número de pieza PC87311A
Descripción Floppy Disk Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de PC87311A (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! PC87311A Hoja de datos, Descripción, Manual

October 1993
PC87311A PC87312 (SuperI OTM II III)
Floppy Disk Controller with Dual UARTs
Parallel Port and IDE Interface
General Description
The PC87311A 12 incorporates a floppy disk controller
(FDC) two full function UARTs a bidirectional parallel port
and IDE interface control logic in one chip The PC87311A
includes standard AT XT address decoding for on-chip
functions and a Configuration Register offering a single
chip solution to the most commonly used IBM PC
PC-XT and PC-AT peripherals The PC87312 includes
standard AT address decoding for on-chip functions and a
Configuration Register set offering a single chip solution to
the most commonly used ISA EISA and Micro Channel pe-
ripherals
The on-chip FDC is software compatible to the PC8477
which contains a superset of the DP8473 and NEC mPD765
and the N82077 floppy disk controller functions The on-
chip analog data separator requires no external compo-
nents and supports the 4 Mb drive format as well as the
other standard floppy drives used with 5 25 and 3 5 me-
dia
In the PC87311A the UARTs are equivalent to two
INS8250N-Bs or NS16450s The bidirectional parallel port
maintains complete compatibility with the IBM PC XT and
AT In the PC87312 the UARTs are equivalent to two
NS16450s or PC16550s The bidirectional parallel port
maintains complete compatibility with the ISA EISA and Mi-
cro Channel parallel ports
The IDE control logic provides a complete IDE interface ex-
cept for the signal buffers The Configuration Registers con-
sist of three byte-wide registers An Index and a Data Regis-
ter which can be relocated within the ISA I O address space
access the Configuration Registers
Features
Y 100% compatible with IBM PC XT and AT architec-
tures (PC87311A) or ISA EISA and Micro Channel ar-
chitectures (PC87312)
Y FDC
Software compatible with the DP8473 the 765A and
the N82077
16-byte FIFO (default disabled)
Burst and Non-Burst modes
Perpendicular Recording drive support
High performance internal analog data separator (no
external filter components required)
Low power CMOS with power down mode
Y UARTs
Software compatible with the INS8250N-B and the
NS16450 (PC87311A) or PC16550A and PC16450
(PC87312)
Y Parallel Port
Bidirectional under either software or hardware
control
Compatible with all IBM PC XT and AT architectures
(PC87311A) or all ISA EISA and Micro Channel ar-
chitectures (PC87312)
Back Voltage protection circuit against damage
caused when printer is powered up
Y IDE Control Logic
Provides a complete IDE interface except for option-
al buffers
Y Address Decoder
Provides selection of all primary and secondary ISA
addresses including COM 1 – 4
Y 100-pin PQFP package
The PC87311A and PC87312 are pin compatible
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
SuperI OTM is a trademark of National Semiconductor Corporation
IBM PC PC-AT PC-XT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL F 11362
TL F 11362 – 1
RRD-B30M75 Printed in U S A

1 page




PC87311A pdf
Basic Configuration
Note PC87311A only
TL F 11362 – 2
5

5 Page





PC87311A arduino
1 0 Pin Description (Continued)
Symbol Pin I O
Function
SOUT1 2 73 65 O Serial Output This output sends composite serial data to the communications link (peripheral device
MODEM or data set) The SOUT signal is set to a marking state (logic 1) after a Master Reset
operation (See BOUT and CFG0 – 4 for further information on these pins )
STB
95 O Data Strobe This output indicates to the printer that valid data is available at the printer port This pin
will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit
The system should pull this pin high using a 4 7 kX resistor
STEP
40 O Step This output signal issues pulses to the disk drive at a software programmable rate to move the
head during a seek operation
TC 6 I Terminal Count Control signal from the DMA controller to indicate the termination of a DMA transfer
TC is accepted only when DACK is active TC is active high in PC-AT and Model 30 modes and active
low in PS 2 mode
TRK0
37 I Track 0 This input indicates to the controller that the head of the selected floppy disk drive is at track
zero
VDDA
33
Analog Supply This pin is the 5V supply for the analog data separator
VDDB C 50 99
Digital Supply This is the 5V supply voltage for the digital circuitry
VSSA
31
Analog Ground This is the analog ground for the data separator
VSSB-E 42 9
90 61
Digital Ground This is the ground for the digital circuitry
WR 18 I Write Active low input to signal a write from the microprocessor to the controller
WDATA 39 O Write Data This output is the write precompensated serial data that is written to the selected floppy
disk drive Precompensation is software selectable
WGATE 38 O Write Gate This output signal enables the write circuitry of the selected disk drive WGATE has been
designed to prevent glitches during power up and power down This prevents writing to the disk when
power is cycled
WP 36 I Write Protect This input indicates that the disk in the selected drive is write protected
X1 OSC
7
I Crystal1 Clock One side of an external 24 MHz crystal is attached here If a crystal is not used a TTL
or CMOS compatible clock is connected to this pin
X2 8 O Crystal2 One side of an external 24 MHz crystal is attached here This pin is left unconnected if an
external clock is used
XTSEL
63 I XT Select When this pin is high during reset the chip will operate in the XT mode When this pin is low
during reset the chip will operate in the AT mode An internal pull-down resistor of 40 kX is on this pin
Use a 10 kX resistor to pull this pin to the required level during reset
There are five differences between AT and XT mode One concerns hard disk operation and the other
four concern UART operation In AT mode the IDE hard drive chip selects (HCS0 HCS1) will be active
for addresses 1F0–7H and 3F6 7H respectively In XT mode the IDE chip select HCS0 responds to
addresses 320–3H and HCS1 is inactive The differences in UART operation are the function of LSR
bit (see Section 6 5 bit 6) the modem control outputs during loop back mode (see Section 6 8 bit 4) the
Scratch Pad Register (see Section 6 10) and the availability of edge (XT) or level (AT) sensitive UART
interrupts
Note XTSEL is an option for the PC87311A only
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet PC87311A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
PC87311PC87311A/PC87312 (SuperI/OTM II/III) Floppy Disk Controller with Dual UARTs/ Parallel Port/ and IDE InterfaceNational Semiconductor
National Semiconductor
PC87311AFloppy Disk ControllerNational Semiconductor
National Semiconductor
PC87311AVFFloppy Disk ControllerNational Semiconductor
National Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar