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PDF PC87303VUL Data sheet ( Hoja de datos )

Número de pieza PC87303VUL
Descripción PC87303VUL SuperI/OTM Sidewinder Lite Floppy Disk Controller/ Keyboard Controller/ Real-Time Clock/ Dual UARTs/ IEEE 1284 Parallel Port/ and IDE Inter
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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PRELIMINARY
February 1995
PC87303VUL SuperI OTM Sidewinder Lite
Floppy Disk Controller Keyboard Controller
Real-Time Clock Dual UARTs IEEE 1284 Parallel Port
and IDE Interface
General Description
The PC87303VUL is a single chip solution incorporating a
Keyboard and PS 2 Mouse Controller (KBC) Real Time
Clock (RTC) and most commonly used I O peripherals in
ISA EISA and MicroChannel based computers In addition
to the KBC and RTC a Floppy Disk Controller (FDC) two
full featured UARTs an IEEE 1284 compatible parallel port
and all the necessary control logic for an IDE interface pro-
vides support for most commonly used I O peripherals
Standard PC-AT address decoding for all the peripherals
a set of configuration registers and two user selectable chip
selects are also implemented in this highly integrated mem-
ber of the SuperI O family The advanced features and high
integration of the PC87303 result in several benefits for low
cost high performance systems Printed circuit board space
savings fewer components on the motherboard and com-
patibility with the latest industry standard peripherals are
only a few of the benefits of using a PC87303
The KBC is fully software compatible with the 8042AH mi-
crocontroller It contains system timing control logic cus-
tom ROM program memory RAM data memory and 18 pro-
grammable I O lines necessary to implement dedicated
control functions It is an efficient controller which uses pre-
dominantly single byte instructions with support for binary and
BCD arithmetic and extensive bit handling capabilities
(Continued)
Features
Y The Floppy Disk Controller
Software compatible with the DP8477 the 765A and
the N82077
16-byte FIFO (disabled by default)
Burst and Non-Burst modes
Perpendicular Recording drive support
High performance internal analog data separator
(no external filter components required)
Low power CMOS with power-down mode
Automatic media-sense support with full IBM TDR
(Tape Drive Register) implementation for PC-AT and
PS 2 floppy drive types
Y The Keyboard Controller
8042AH and PC87911 software compatible
8-bit Microcomputer with 2 kbytes custom ROM and
256 bytes data RAM
Asynchronous access to two data registers and one
status register during normal operation
Dedicated open drain outputs for keyboard controller
application
Supports both interrupt and polling
Supports DMA handshake
18 programmable I O pins
4 dedicated open-drain outputs
8-bit Timer Counter
Binary and BCD arithmetic
Expandable I O
(Continued)
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
SuperI OTM is a trademark of National Semiconductor Corporation
MicroChannel PC-AT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL C 12074
TL C 12074 – 1
RRD-B30M75 Printed in U S A

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PC87303VUL pdf
List of Figures
FIGURE 2-1 PC87303 Configuration Registers
FIGURE 2-2 PC87303 Four Floppy Drive Circuit
FIGURE 3-1 FDC Functional Block Diagram
FIGURE 4-1 FDC Command Structure
FIGURE 4-2 IBM Perpendicular and ISO Formats Supported by Format Command
FIGURE 5-1 FDC Data Separator Block Diagram
FIGURE 5-2 PC87303 Dynamic Window Margin Performance
FIGURE 5-3 Read Data Algorithm State Diagram
FIGURE 5-4 Perpendicular Recording Drive R W Head and Pre-Erase Head
FIGURE 6-1 PC87303 Composite Serial Data
FIGURE 6-2 Receiver FIFO Trigger Level
FIGURE 7-1 EPP 1 7 Address Write
FIGURE 7-2 EPP 1 7 Address Read
FIGURE 7-3 EPP Write with ZWS
FIGURE 7-4 EPP 1 9 Address Write
FIGURE 7-5 EPP 1 9 Address Read
FIGURE 7-6 ECP Forward Write Cycle
FIGURE 7-7 ECP Backward Read Cycle
FIGURE 8-1 IDE Interface Signal Equations (Non-DMA)
FIGURE 9-1 Keyboard Controller Functional Block Diagram
FIGURE 9-2 Keyboard Controller to Host System Interface
FIGURE 9-3 Status Register
FIGURE 9-4 PSW Register Bits
FIGURE 9-5 Keyboard Controller Data Memory Map
FIGURE 9-6 Keyboard Controller Stack Organization
FIGURE 9-7 Active Pull-Up I O Port Structure
FIGURE 9-8 Using Port Pins as Inputs
FIGURE 9-9 Timing Generation and Timer Circuit
FIGURE 9-10 Internal Clock Connection
FIGURE 9-11 External Clock Connection
FIGURE 9-12 Instruction Cycle Timing
FIGURE 9-13 Oscillator Internal and External Circuitry
FIGURE 9-14 Interrupt Status Timing
FIGURE 9-15 Typical Battery Configuration
FIGURE 9-16 Typical Battery Current During Battery Backed Mode
FIGURE 10-1 Clock Timing
FIGURE 10-2 Microprocessor Read Timing
FIGURE 10-3 Microprocessor Write Timing
FIGURE 10-4 Read after Write Operation to All Registers and RAM Timing
FIGURE 10-5 Baud Out Timing
FIGURE 10-6 Transmitter Timing
FIGURE 10-7 Sample Clock Timing
FIGURE 10-8 Receiver Timing
FIGURE 10-9 FIFO Mode Receiver Timing
FIGURE 10-10 Timeout Receiver Timing
FIGURE 10-11 MODEM Control Timing
FIGURE 10-12a FDC DMA Timing
FIGURE 10-12b ECP DMA Timing
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PC87303VUL arduino
1 0 Pin Description (Continued)
TABLE 1-1 Pin Descriptions (Alphabetical) (Continued)
Symbol
Pin I O
Function
DCD1 2
114 106 I Data Carrier Detect When low this signal indicates that the MODEM or data set has detected the
data carrier The DCD signal is a MODEM status input whose condition the CPU can test by reading
bit 7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 7 is the
complement of the DCD signal Bit 3 (DDCD) of the MSR indicates whether the DCD input has
changed state since the previous reading of the MSR
Note Whenever the DDCD bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
DENSEL
77 O Density Select Indicates that a high FDC density data rate (500 kbps or 1 Mbps) or a low density
data rate (250 kbps or 300 kbps) is selected DENSEL is active high for high density (5 25 drives)
when IDENT is high and active low for high density (3 5 drives) when IDENT is low DENSEL is
also programmable via the Mode command (see Section 4 2 6)
DIR 69 O Direction This output determines the direction of the floppy disk drive (FDD) head movement
(active e step in inactive e step out) during a seek operation During reads or writes DIR is
inactive
DR0 1
73 74
O Drive Select 0 1 These are the decoded Drive Select outputs that are controlled by the Digital
Output Register bits D0 D1 The Drive Select outputs are gated with DOR bits 4 – 7 These are
active low outputs They are encoded with information to control four FDDs when bit 4 of the
Function Enable Register (FER) is set (See MTR0 1 for more information )
DR23
78 O Drive 2 or 3 DR23 is asserted when either Drive 2 or Drive 3 is accessed (except during logical
drive exchange see bit 3 of TDR) This pin is configured when bit 1 of ASC is 1 (See DRV2 for
further information )
DRATE0 1 83 82
O Data Rate 0 1 These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the
Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was
written to last) These pins are totem-pole buffered outputs (6 mA sink 6 mA source) (See
MSEN0 1 for further information )
DRID0 1
90 87
I Drive ID These pins accept input from the floppy disk drive which indicates the type of drive in use
These pins should be tied low if they are not used DRID0 1 is configured when bit 2 of ASC is 1
(See IOCS16 IDEHI and VLD0 for further information )
DRV2
78 I Drive2 This input indicates whether a second floppy disk drive has been installed The state of this
pin is available from Status Register A in PS 2 mode This pin is confgured when bit 1 of ASC is 0
(See DR23 for further information )
DSKCHG 60 I Disk Change This input indicates if the drive door has been opened The state of this pin is
available from the Digital Input register This pin can also be configured as the Read Gate (RGATE)
data separator diagnostic input via the Mode command (see Section 4 2 6)
DSR1 2
113 105 I Data Set Ready When low this signal indicates that the data set or MODEM is ready to establish a
communications link The DSR signal is a MODEM status input whose condition the CPU can test
by reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is
the complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has
changed state since the previous reading of the MSR
Note Whenever the DDSR bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
DSTRB
116 O Data Strobe This signal is used in EPP mode as a data strobe It is active low (See AFD and
Table 7-5 for further information )
DTR1 2
108 98
O Data Terminal Ready When low this output indicates to the MODEM or data set that the UART is
ready to establish a communications link The DTR signal can be set to an active low by
programming bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation
sets this signal to its inactive (high) state Loop mode operation holds this signal to its inactive state
(See CFG0–4 for further information )
ERR
117 I Error A connected printer sets this input low when it has detected an error This pin has a nominal
25 kX pull-up resistor attached to it
FDACK
28 I DMA Acknowledge Active low input to acknowledge the FDC DMA request and enable the RD
and WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is enabled by
bit D3 of the Digital Output Register (DOR) When in PS 2 mode FDACK is always enabled and bit
D3 of the DOR is reserved FDACK should be held high during I O accesses
11

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