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PDF PC8477B Data sheet ( Hoja de datos )

Número de pieza PC8477B
Descripción Advanced Floppy Disk Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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August 1993
PC8477B (SuperFDCTM)
Advanced Floppy Disk Controller
General Description
The PC8477B CMOS advanced floppy disk controller is an
enhanced version of National’s DP8473 floppy controller
The PC8477B is software compatible with the DP8473 and
NEC mPD765 floppy disk controllers In addition it is pin and
software compatible with the Intel 82077AA floppy control-
ler The PC8477B a 24 MHz crystal a device chip select
and a resistor package are all that is needed for a complete
PC-AT PS 2 or EISA floppy controller solution
The PC8477B includes advanced features such as a
16 byte FIFO (Burst and Non-Burst modes) support of Per-
pendicular Recording Mode disk drives PS 2 diagnostic
registers for Model 30 and Models 50 60 80 standard
CMOS disk I O and additional commands to control these
new features The 16 byte FIFO will increase system per-
formance at higher data rates and with multi-tasking bus
structures This controller is designed to fit into all PC-AT
EISA and PS 2 designs as well as other advanced applica-
tions
Features
Y Pin and software compatible with Intel 82077AA FDC
Y Software compatible with NSC’s DP8473
Y 16 byte FIFO (default disabled)
Burst and Non-Burst modes
Programmable threshold
Y Perpendicular Mode Recording drive support
Y High performance internal analog data separator (no
external filter components required)
Y Low power CMOS with manual power down mode
Y Automatic power down mode for complete software
transparency
Y Integrates all PC-AT and PS 2 logic
On chip Oscillator
PC compatible FDC address decode
PS 2 Model 30 and Model 50 60 80 diagnostic
registers
DMA control circuitry
High current CMOS disk interface outputs
Data Rate and Digital Output registers
12 mA mP bus interface buffers
Y Data Rate Support 250 300 kb s 500 kb s
and 1 Mb s
Y Write precompensation software programmable
Y 68 pin PLCC package
Y 60 pin PQFP package
Ideal for space limited applications
Functional Block Diagram
FIGURE 1-1
SuperFDCTM is a trademark of National Semiconductor Corporation
TRI-STATE is a registered trademark of National Semiconductor Corporation
IBM PC-AT and PS 2 are registered trademarks of International Business Machines Corp
C1995 National Semiconductor Corporation TL F 11332
TL F 11332 – 3
RRD-B30M75 Printed in U S A

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PC8477B pdf
Connection Diagrams
Plastic Chip Carrier (V)
Order Number PC8477BV-1
See NS Package Number V68A
TL F 11332 – 1
Plastic Quad Flat Package (VF)
Order Number PC8477BVF-1
See NS Package Number VF60A
FIGURE 1-2
5
TL F 11332 – 2

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PC8477B arduino
3 0 Register Description (Continued)
3 4 DRIVE REGISTER (TDR) Read Write
This register is used to assign a particular drive number with
the tape drive support mode of the data separator All other
logical drives are assigned floppy drive support with the
data separator Any future reference to the assigned tape
drive will invoke tape drive support The TDR is unaffected
by a software reset
TDR
D7 D6 D5 D4 D3 D2 D1 D0
DESC X X X X X X TAPE TAPE
SEL1 SEL0
RESET
COND
NA
NA
NA
NA
NA
NA
0
0
D7 – D2
D1 – D0
Reserved These bits are ignored when written
to and are TRI-STATE when read
Tape Select 1 0 These two bits assign a logical
drive number to be a tape drive Drive 0 is not
available as a tape drive and is reserved as the
floppy disk boot drive See Table 3-3 for the
tape drive assignment values
TABLE 3-3 Tape Drive Assignment Values
TAPESEL1
0
0
1
1
TAPESEL0
0
1
0
1
DRIVE
SELECTED
None
1
2
3
3 5 MAIN STATUS REGISTER (MSR) Read Only
The read only Main Status Register indicates the current
status of the disk controller The Main Status Register is
always available to be read One of its functions is to control
the flow of data to and from the Data Register (FIFO) The
Main Status Register indicates when the disk controller is
ready to send or receive data through the Data Register It
should be read before each byte is transferred to or from
the Data Register except during a DMA transfer No delay is
required when reading this register after a data transfer
After a hardware or software reset or recovery from a pow-
er down state the Main Status Register is immediately avail-
able to be read by the mP It will contain a value of 00 hex
until the oscillator circuit has stabilized and the internal reg-
isters have been initialized When the PC8477B is ready to
receive a new command it will report an 80 hex to the mP
The system software can poll the MSR until it is ready The
worst case time allowed for the MSR to report an 80 hex
value (RQM set) is 2 5 ms after reset or power up
MSR
D7 D6 D5 D4 D3 D2 D1 D0
DESC RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0
DMA PROG BUSY BUSY BUSY BUSY
RESET
COND
0
0
0
0
0
0
0
0
D7 Request for Master Indicates that the control-
ler is ready to send or receive data from the mP
through the FIFO This bit is cleared immediate-
ly after a byte transfer and will become set
again as soon as the disk controller is ready for
the next byte During a Non-DMA Execution
phase the RQM indicates the status of the in-
terrupt pin
D6 Data I O (Direction) Indicates whether the
controller is expecting a byte to be written to (0)
or read from (1) the Data Register
D5 Non-DMA Execution Indicates that the con-
troller is in the Execution Phase of a byte trans-
fer operation in the Non-DMA mode Used for
multiple byte transfers by the mP in the Execu-
tion Phase through interrupts or software poll-
ing
D4 Command in Progress This bit is set after the
first byte of the Command Phase is written This
bit is cleared after the last byte of the Result
Phase is read If there is no Result Phase in a
command the bit is cleared after the last byte
of the Command Phase is written
D3 Drive 3 Busy Set after the last byte of the
Command Phase of a Seek or Recalibrate com-
mand is issued for drive 3 Cleared after reading
the first byte in the Result Phase of the Sense
Interrupt Command for this drive
D2 Drive 2 Busy Same as above for drive 2
D1 Drive 1 Busy Same as above for drive 1
D0 Drive 0 Busy Same as above for drive 0
3 6 DATA RATE SELECT REGISTER (DSR) Write Only
This write only register is used to program the data rate
amount of write precompensation power down mode and
software reset The data rate is programmed via the CCR
not the DSR for PC-AT and PS 2 Model 30 and MicroChan-
nel applications Other applications can set the data rate in
the DSR The data rate of the floppy controller is deter-
mined by the most recent write to either the DSR or CCR
The DSR is unaffected by a software reset A hardware re-
set will set the DSR to 02 (hex) which corresponds to the
default precompensation setting and 250 kb s
DSR
D7 D6 D5 D4 D3 D2
D1
D0
S W LOW PRE- PRE- PRE-
DESC RESET PWR 0 COMP2 COMP1 COMP0 DRATE1 DRATE0
RESET
COND
0
00 0
0
0
1
0
D7 Software Reset A 1 in this bit location will re-
set the part similar to the DOR RESET (D2) ex-
cept that this software reset is self-clearing
D6 Low Power A 1 to this bit will put the controller
into the Manual Low Power mode The oscilla-
tor and data separator circuits will be turned off
Manual Low Power can also be accessed via
the Mode command The chip will come out of
low power after a software reset or access to
the Data Register or Main Status Register
11

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