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PDF PC66-222-920 Data sheet ( Hoja de datos )

Número de pieza PC66-222-920
Descripción 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
Fabricantes Siemens Semiconductor Group 
Logotipo Siemens Semiconductor Group Logotipo



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No Preview Available ! PC66-222-920 Hoja de datos, Descripción, Manual

3.3V 2M x 64/72-Bit 1 BANK SDRAM Module
3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
168 pin unbuffered DIMM Modules
HYS64/72V2200GU-8/-10
HYS64/72V4220GU-8/-10
168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation
Optimized for byte-write non-parity or ECC applications
JEDEC standard Synchronous DRAMs (SDRAM)
Fully PC board layout compatible to INTELs’ Rev. 1.0 module specification
SDRAM Performance:
fCK Clock frequency (max.)
tAC Clock access time
Programmed Latencies :
-8 -8-3 -10
100 100
66
66
8
Units
MHz
ns
Product Speed
-8 PC100
-8-3 PC100
-10 PC66
CL
2
3
2
tRCD
2
2
2
tRP
2
3
2
Single +3.3V(± 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E2PROM
Utilizes 2M x 8 SDRAMs in TSOPII-44 packages
4096 refresh cycles every 64 ms
133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads
Semiconductor Group
1
6.98

1 page




PC66-222-920 pdf
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
CS1
CS0
DQMB0
DQ(7:0)
DQMB1
DQ(15:8)
CB(7:0)
CS3
CS2
DQMB2
DQ(23:16)
DQMB3
DQ(31:24)
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D0 D8
DQMB4
DQ(39:32)
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D1 D9
DQMB5
DQ(47:40)
CS
DQM
CS
DQM
DQ0-DQ7 DQ0-DQ7
D16 D17
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D2 D10
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D3 D11
DQMB6
DQ(55:48)
DQMB7
DQ(63:56)
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D4 D12
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D5 D13
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D6 D14
CS CS
DQM
DQM
DQ0-DQ7 DQ0-DQ7
D7 D15
A0-A10,BA
D0 - D15,(D16,D17)
VDD
VSS
C0-C31,(C32..C35)
D0 - D15,(D16,D17)
D0 - D7,(D8)
E2PROM (256wordx8bit)
SA0
SA1
SA0
SA1 SDA
SA2 SA2 WP
SCL
SCL
47k
RAS, CAS, WE
CKE0
CKE1
VDD
10k
D0 - D15,(D16,D17)
D0 - D7,(D16)
D9 - D15,(D17)
CLK0
CLK1
CLK2
CLK3
Clock Wiring
4M x 64
4M x 72
4 SDRAM+3.3pF 5 SDRAM
4 SDRAM+3.3pF 5 SDRAM
4 SDRAM+3.3pF 4 SDRAM+3.3pF
4 SDRAM+3.3pF 4 SDRAM+3.3pF
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.
Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU)
Semiconductor Group
5

5 Page





PC66-222-920 arduino
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence
detect protocol ( I2C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
0 Number of SPD bytes
1 Total bytes in Serial PD
2 Memory Type
3 Number of Row Addresses (without BS bits)
4 Number of Column Addresses
(for x8 SDRAM)
5 Number of DIMM Banks
6 Module Data Width
7 Module Data Width (contd’ )
8 Module Interface Levels
9 SDRAM Cycle Time at CL=3
10 SDRAM Access time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
13 SDRAM width, Primary
14 Error Checking SDRAM data width
15 Minimum clock delay for back-to-back ran-
dom column address
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
20 WE Latencies
21 SDRAM DIMM module attributes
22 SDRAM Device Attributes :General
23 Min. Clock Cycle Time at CAS Latency = 2
24 Max. data access time from Clock for CL=2
25 Minimum Clock Cycle Time at CL = 1
26 Maximum Data Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
28 Minimum Row Active to Row Active delay
tRRD
SPD Entry Value
128
256
SDRAM
11
9
1/2
64 / 72
0
LVTTL
10.0 ns
6.0 ns
none / ECC
Self-Refresh,
15.6µs
x8
n/a / x8
tccd = 1 CLK
1, 2, 4, 8 & full page
2
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
10.0 ns
6.0 ns
not supported
not supported
20 ns
16 ns
2Mx64
-8
80
08
04
0B
09
01
40
00
01
A0
60
00
80
08
00
01
8F
02
06
01
01
00
06
A0
60
FF
FF
14
10
Hex
2Mx72 4Mx64
-8 -8
80 80
08 08
04 04
0B 0B
09 09
01 02
48 40
00 00
01 01
A0 A0
60 60
02 00
80 80
08 08
08 00
01 01
8F 8F
02 02
06 06
01 01
01 01
00 00
06 06
A0 A0
60 60
FF FF
FF FF
14 14
10 10
4Mx72
-8
80
08
04
0B
09
02
48
00
01
A0
60
02
80
08
08
01
8F
02
06
01
01
00
06
A0
60
FF
FF
14
10
Semiconductor Group
11

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